<div dir="ltr">Yes, the arch is just as you said, something like AMD GPU, but Intel GPU don't have separate register file for 'scalar/vector'.<div>In fact my idea of defining the register tuples was borrowed from SIRegisterInfo.td in AMD GPU.<br></div><div>But seems that AMD GPU mainly support i32/i64 register type, while Intel GPU also support byte/short register type.</div><div>So I have to start defining the registers from 'byte' type, and then build up other type registers through RegisterTuples.<br><div>I thought RegisterTuple is kind of expressing register alias in RegisterInfo.td file. I am not sure whether I understand it correctly. My first trial was like below(to make things simple, I remove some WORD/QWORD register class):</div><div><div>let Namespace = "IntelGPU" in {</div><div><br></div><div>foreach Index = 0-15 in {</div><div> def sub#Index : SubRegIndex<32, !shl(Index, 5)>;</div><div>}</div><div>}</div><div><br></div><div>class IntelGPUReg<string n, bits<13> regIdx> : Register<n> {</div><div> bits<2> HStride;</div><div> bits<1> regFile;</div><div><br></div><div> let Namespace = "IntelGPU";</div><div> let HWEncoding{12-0} = regIdx;</div><div> let HWEncoding{15} = regFile;</div><div>}</div><div>// here I define the whole 4096 byte registers</div><div>foreach Index = 0-4095 in {</div><div> def Rb#Index : IntelGPUReg <"Rb"#Index, Index> {</div><div> let regFile = 0;</div><div> }</div><div>}</div><div><br></div><div>// b-->byte w-->word d-->dword q-->qword</div><div>// the set of uniform byte register</div><div>def gpr_b : RegisterClass<"IntelGPU", [i8], 8,</div><div> (sequence "Rb%u", 0, 4095)> {</div><div> let AllocationPriority = 1;</div><div>}</div><div><br></div><div>def gpr_d : RegisterTuples<[sub0, sub1, sub2, sub3],</div><div> [(add (decimate gpr_b, 4)),</div><div> (add (decimate (shl gpr_b, 1), 4)),</div><div> (add (decimate (shl gpr_b, 2), 4)),</div><div> (add (decimate (shl gpr_b, 3), 4))]>;</div><div><br></div><div>// simd byte use stride 2 register as stride 1 does not support useful ALU instruction</div><div>def gpr_b_simd8 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],</div><div> [(add (decimate gpr_b, 16)),</div><div> (add (decimate (shl gpr_b, 2), 16)),</div><div> (add (decimate (shl gpr_b, 4), 16)),</div><div> (add (decimate (shl gpr_b, 6), 16)),</div><div> (add (decimate (shl gpr_b, 8), 16)),</div><div> (add (decimate (shl gpr_b, 10), 16)),</div><div> (add (decimate (shl gpr_b, 12), 16)),</div><div> (add (decimate (shl gpr_b, 14), 16))]>;</div><div><span class="" style="white-space:pre"> </span> </div><div>def gpr_d_simd8 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],</div><div> [(add (decimate gpr_d, 8)),</div><div> (add (decimate (shl gpr_d, 1), 8)),</div><div> (add (decimate (shl gpr_d, 2), 8)),</div><div> (add (decimate (shl gpr_d, 3), 8)),</div><div> (add (decimate (shl gpr_d, 4), 8)),</div><div> (add (decimate (shl gpr_d, 5), 8)),</div><div> (add (decimate (shl gpr_d, 6), 8)),</div><div> (add (decimate (shl gpr_d, 7), 8))]>;</div><div>def RegD_Uniform : RegisterClass<"IntelGPU", [i32, f32], 32, (add gpr_d)>;</div><div>def RegD_SIMD8 : RegisterClass<"IntelGPU", [i32, f32], 32, (add gpr_d_simd8)> {</div><div>}</div></div><div>This is easy for me to define the register alias information. But it won't works!</div><div>the tablegen exit and tells me: "error:Ran out of lanemask bits to represent subregister sub1_then_sub1"</div><div>Anybody know what's wrong here?</div></div><div><br></div><div>- Ruiling</div></div><div class="gmail_extra"><br><div class="gmail_quote">2016-08-23 11:45 GMT+08:00 <span dir="ltr"><<a href="mailto:escha@apple.com" target="_blank">escha@apple.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word">If I understand right, on this arch, ‘uniform’ refers to values that only take one lane of register file instead of SIMD-width lanes, and they *share* the same region of the register file as non-uniform values. This is in contrast to e.g. AMDGPU where SGPRs (scalar GPRs) and VGPRs are separate register files.<div><br></div><div>If this understanding is correct, you may be able to define uniform and non-uniform registers separately, but make sure that one aliases the other, e.g. so that (if your SIMD width is 16) VGPR 20 overlaps SGPR 320, 321….335. So you can have 128 vector registers, 16*128 uniforms, or a mix of the two.</div><div><br></div><div>(Maybe some of the AMDGPU maintainers have thoughts?)</div><div><br></div><div>—escha<div><div class="h5"><br><div><br><div><blockquote type="cite"><div>On Aug 22, 2016, at 8:07 PM, Ruiling Song <<a href="mailto:ruiling.song83@gmail.com" target="_blank">ruiling.song83@gmail.com</a>> wrote:</div><br><div><div dir="ltr"><span style="font-size:14px">Hi </span><span style="font-size:14px;background-color:rgb(255,255,255)">Escha</span><span style="font-size:14px">,</span><div style="font-size:14px"><br></div><div style="font-size:14px">Great to have your comment! Do you have any specific reason for not doing like this?</div><div style="font-size:14px">I am not sure whether I understand your point correctly. For "just model one thread",</div><div style="font-size:14px">do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"??</div><div style="font-size:14px"><br></div><div style="font-size:14px">For my case, may be something like I only need to define r0~r127 as register for i32 register (each r# is just enough for simd8 i32).</div><div style="font-size:14px">Then the register allocator never need to go to allocate the sub-registers, just operate them as a whole. right?</div><div style="font-size:14px"><br></div><div style="font-size:14px">Yes, it looks really easy for divergent registers. But I think then I would lose the ability</div><div style="font-size:14px">to allocate uniform register. Am I right? Is there any way to allocate uniform register</div><div style="font-size:14px">as well as allocate divergent register?<div class="gmail_extra"><br></div><div class="gmail_extra">Thanks!</div><div class="gmail_extra">Ruiling</div></div><div class="gmail_extra"><br><div class="gmail_quote">2016-08-23 0:32 GMT+08:00 <span dir="ltr"><<a href="mailto:escha@apple.com" target="_blank">escha@apple.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word"><br><div><span><blockquote type="cite"><div>On Aug 22, 2016, at 6:46 AM, Ruiling Song via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:</div><br><div><div dir="ltr"><div>Hello Everyone,</div><div><br></div><div>I am trying to make a new LLVM backend target for Intel GPU.<br>I would start from targeting OpenCL language first.</div><div>But I am not quite familiar with LLVM backend infrastructure.</div><div>I have some problem on describing the RegisterInfo.<br><br></div><div>Intel GPU launches lots of hardware threads to do GPGPU workload.</div><div>Each hardware thread has 128 registers(r0-r127), with each one of size 32 byte.<br></div><div>Each hardware thread may run in SIMD 8/16/32 way, which maps to</div><div>8/16/32 OpenCL working items. And the SIMD width is chosen at</div><div>compile time (normally chosen according to register pressure, bigger simd width means bigger register pressure).</div><div>Note each instruction has each own exec-width, which may not be equal to program SIMD width.</div><div>Normally we would allocate contiguous registers for divergent value.</div><div>For example, we have a program compiled as SIMD 8, we need to allocate 4 byte*8=32 byte</div><div>value for a divergent float/i32 value. But if there is a 'short type' value,</div><div>it only needs 2 byte*8=16 byte, that is half of a 32-byte-register.<br></div><div>we may also allocate for 'uniform' value, a uniform value only needs type-sized register,</div><div>without multiply 'simd-width'. A uniform float/i32 value only needs 4 byte physical register.</div><div>Thus a 32-byte-register can hold up to 8 different uniform float/i32 values.<br></div></div></div></blockquote><div><br></div></span><div>As a GPU backend maintainer, I strongly discourage trying to model the total register bank of the GPU in LLVM. Just model one thread. This will make things much, much easier.</div><span><blockquote type="cite"><div dir="ltr"><div></div></div></blockquote><br></span></div><div>—escha</div></div></blockquote></div><br></div></div>
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