<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Aug 22, 2016, at 11:54, Phil Tomson <<a href="mailto:phil.a.tomson@gmail.com" class="">phil.a.tomson@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><br class="Apple-interchange-newline"><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><div class="gmail_quote" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">On Mon, Aug 22, 2016 at 11:40 AM, Matt Arsenault<span class="Apple-converted-space"> </span><span dir="ltr" class=""><<a href="mailto:arsenm2@gmail.com" target="_blank" class="">arsenm2@gmail.com</a>></span><span class="Apple-converted-space"> </span>wrote:<br class=""><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-style: solid; border-left-color: rgb(204, 204, 204); padding-left: 1ex;"><div class=""><div class="h5"><br class="">> On Aug 22, 2016, at 11:20, Phil Tomson via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:<br class="">><br class="">> We improved our instruction itineraries and now we're seeing our testcases for fence instructions break.<br class="">><br class="">> For example, we have this testcase:<br class="">><br class="">> @write_me = external global i32<br class="">> @read_me = external global i32<br class="">><br class="">> ; Function Attrs: nounwind<br class="">> define i32 @xstg_intrinsic(i32 %foo) #0 {<br class="">> entry:<br class="">> ; CHECK: store r0, r1, 0, 32<br class="">> ; CHECK-NEXT: fence 2<br class="">> %foo.addr = alloca i32, align 4<br class="">> store i32 %foo, i32* %foo.addr, align 4<br class="">> %0 = load i32* %foo.addr, align 4<br class="">> store volatile i32 %0, i32* @write_me, align 4<br class="">> call void @llvm.xstg.memory.barrier(i32 2, i8 0)<br class="">> %1 = load volatile i32* @read_me, align 4<br class="">> ret i32 %1<br class="">> }<br class="">><br class="">> Prior to adding our instruction itineraries the code generated was:<br class="">><br class="">> xstg_intrinsic: # @xstg_intrinsic<br class="">> # BB#0: # %entry<br class="">> subI r509, r509, 16, 64<br class="">> store r510, r509, 0, 64<br class="">> bitop1 r510, r509, 0, OR, 64<br class="">> store r0, r510, 12, 32<br class="">> movimm r1, %hi(write_me), 64<br class="">> movimmshf32 r1, r1, %lo(write_me)<br class="">> store r0, r1, 0, 32<br class="">> fence 2<br class="">> movimm r0, %hi(read_me), 64<br class="">> movimmshf32 r0, r0, %lo(read_me)<br class="">> load r1, r0, 0, 32<br class="">> bitop1 r509, r510, 0, OR, 64<br class="">> load r510, r509, 0, 64<br class="">> addI r509, r509, 16, 64<br class="">> jabs r511<br class="">><br class="">> Note the separation between the store prior to the fence and the code that comes after.<br class="">><br class="">> Now that we've got itineraries in place we see:<br class="">><br class="">> subI r509, r509, 16, 64<br class="">> store r510, r509, 0, 64<br class="">> bitop1 r510, r509, 0, OR, 64<br class="">> movimm r1, %hi(write_me), 64<br class="">> store r0, r510, 12, 32<br class="">> movimmshf32 r1, r1, %lo(write_me)<br class="">> movimm r2, %hi(read_me), 64<br class="">> store r0, r1, 0, 32<br class="">> movimmshf32 r2, r2, %lo(read_me)<br class="">> fence 2<br class="">> load r1, r2, 0, 32<br class="">> bitop1 r509, r510, 0, OR, 64<br class="">> load r510, r509, 0, 64<br class="">> addI r509, r509, 16, 64<br class="">> jabs r511<br class="">><br class="">> the movimm which sets up the address for the load has been moved up prior to the fence.<br class="">><br class="">> Is there a way to indicate in the itinerary that position of the fence should be fixed - no instruction reordering "through" the fence/barrier?<br class="">><br class="">> Phil<br class=""></div></div>> ______________________________<wbr class="">_________________<br class="">> LLVM Developers mailing list<br class="">><span class="Apple-converted-space"> </span><a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a><br class="">><span class="Apple-converted-space"> </span><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" rel="noreferrer" target="_blank" class="">http://lists.llvm.org/cgi-bin/<wbr class="">mailman/listinfo/llvm-dev</a><br class=""><br class=""><br class="">I don’t see a change relative to the memory instructions.<span class="Apple-converted-space"> </span></blockquote><div class=""><br class=""></div><div class="">True, we may be being a bit too skiddish about this... perhaps the solution is to change the testcase so that we can ensure that the relative order between the store and the fence has been preserved.<br class=""> <br class=""></div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-style: solid; border-left-color: rgb(204, 204, 204); padding-left: 1ex;">Do you mean you want this to avoid scheduling of any instruction around any other? Does the instruction have isSideEffects set on it?</blockquote><div class=""><br class=""></div><div class="">Where can I find information about isSideEffects? Googling "LLVm isSideEffects" didnt' reveal anything that looked relevant.<br class=""></div></div></div></blockquote><div><br class=""></div><div>hasSideEffects. Look in Target.td / TargetInstrInfo.h. For a memory fence I think it should be sufficient to set mayLoad = 1, mayStore = 1 and not give the fence any memory operands</div><br class=""><blockquote type="cite" class=""><div class=""><div class="gmail_quote" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div class=""> <br class=""></div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-style: solid; border-left-color: rgb(204, 204, 204); padding-left: 1ex;">I think the fallback if that isn’t enough is to override TargetInstrInfo::<wbr class="">isSchedulingBoundary<br class=""><span class=""><font color="#888888" class=""><br class=""></font></span></blockquote><div class=""><br class=""></div><div class="">Thanks, I'll look at that in other targets.<br class=""><br class=""></div><div class="">Phil<span class="Apple-converted-space"> </span><br class=""></div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-style: solid; border-left-color: rgb(204, 204, 204); padding-left: 1ex;"><span class=""><font color="#888888" class="">-Matt</font></span></blockquote></div></div></blockquote></div><br class=""></body></html>