<div dir="ltr"><div><div><div><div><div><div><div><div>Krzysztof, thank you for your response. However, I don't really understand how to fix my problem. Namely, I don't understand how this introduces a cycle in the DAG. Do you have any hints as to what aspect of my TblGen code is broken?<br><br></div>According to my [rather naive] reading of the Selection DAG just before ISEL, the BUILD_VECTOR node has 16 inputs (all inputs are the load - t16). In my pattern, I tried to select exactly that. I would like that node to select to a pair of instructions (along the lines of):<br></div>LXSIBZX 34, 0, 3<br></div>VSPLTB 2, 2, 7<br><br></div>If I specify the pattern as:<br> <span style="font-family:monospace,monospace">def : Pat<(v16i8 (scalar_to_vector ScalarLoads.Li8)),<br> (v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>;</span><br><br></div>and convert the BUILD_VECTOR ISD node to a SCALAR_TO_VECTOR followed by a VECTOR_SHUFFLE, then the match works just fine and the DAG:<br><span style="font-family:monospace,monospace">SelectionDAG has 11 nodes:<br> t0: ch = EntryToken<br> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0<br> t16: i32,ch = load<LD1[%ptr](tbaa=<0x1003ac5f448>), anyext from i8> t0, t2, undef:i64<br> t17: v16i8 = scalar_to_vector t16<br> t19: v16i8 = vector_shuffle<0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0> t17, undef:v16i8<br> t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t19<br> t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1<br></span><br></div>is selected to:<br><span style="font-family:monospace,monospace">SelectionDAG has 12 nodes:<br> t0: ch = EntryToken<br> t17: v16i8,ch = VSPLTBs TargetConstant:i32<7>, t23, t23:1<br> t19: v16i8 = VSPLTB TargetConstant:i32<15>, t17<br> t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t19<br> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0<br> t23: f64,ch = LXSIBZX<Mem:LD1[%ptr](tbaa=<0x1003ac5f448>)> Register:i64 %ZERO8, t2, t0<br> t12: ch = BLR8 Register:v16i8 %V2, t11, t11:1</span><br><br></div>As you can see, the pair of instructions I specified actually loads and splats an i8 value into a vector. So the natural match for that pair is for a BUILD_VECTOR with a LOAD as input (which doesn't work), rather than for a SCALAR_TO_VECTOR with a LOAD as input (which does work).<br></div>If you have any hints as to what I need to fix, I'd appreciate it because I'm kind of at my wit's end with this pattern.<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 1, 2016 at 3:17 PM, Krzysztof Parzyszek via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The MergeInputChains operation verifies if the chains that are inputs to this node can converge to this point. When it fails, it's usually because it would create a cycle in the DAG.<br>
<br>
-Krzysztof<div><div class="h5"><br>
<br>
<br>
On 7/29/2016 12:57 PM, Nemanja Ivanovic via llvm-dev wrote:<br>
</div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div class="h5">
I have the following selection DAG:<br>
SelectionDAG has 9 nodes:<br>
t0: ch = EntryToken<br>
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0<br>
t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8><br>
t0, t2, undef:i64<br>
t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16,<br>
t16, t16, t16, t16, t16, t16, t16, t16<br>
t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15<br>
t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1<br>
<br>
and the following pattern that I'd like to match:<br>
<br>
def ScalarLoads {<br>
dag Li8 = (i32 (extloadi8 xoaddr:$src));<br>
}<br>
<br>
def : Pat<(v16i8 (build_vector ScalarLoads.Li8, ScalarLoads.Li8,<br>
ScalarLoads.Li8, ScalarLoads.Li8,<br>
ScalarLoads.Li8, ScalarLoads.Li8,<br>
ScalarLoads.Li8, ScalarLoads.Li8,<br>
ScalarLoads.Li8, ScalarLoads.Li8,<br>
ScalarLoads.Li8, ScalarLoads.Li8,<br>
ScalarLoads.Li8, ScalarLoads.Li8,<br>
ScalarLoads.Li8, ScalarLoads.Li8)),<br>
(v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>;<br>
<br>
But it doesn't match it. The matching fails at an index that corresponds<br>
to the following line:<br>
OPC_EmitMergeInputChains, 16, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,<br>
14, 15, 16,<br>
<br>
I don't know what that line means. Can someone help?<br>
Thanks.<br>
<br>
<br></div></div>
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