<html><head><style type='text/css'>p { margin: 0; }</style></head><body><div style='font-family: arial,helvetica,sans-serif; font-size: 10pt; color: #000000'><br><hr id="zwchr"><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><b>From: </b>"vivek pandya" <vivekvpandya@gmail.com><br><b>To: </b>"Hal Finkel" <hfinkel@anl.gov><br><b>Cc: </b>"llvm-dev" <llvm-dev@lists.llvm.org>, "Quentin Colombet" <qcolombet@apple.com>, "Mehdi Amini" <mehdi.amini@apple.com><br><b>Sent: </b>Friday, July 29, 2016 5:02:44 AM<br><b>Subject: </b>Re: A thought to improve IPRA<br><br><div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jul 29, 2016 at 9:01 AM, Hal Finkel <span dir="ltr"><<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;"><span><hr id="zwchr"><br>
> From: "vivek pandya" <<a href="mailto:vivekvpandya@gmail.com" target="_blank">vivekvpandya@gmail.com</a>><br>
> To: "Mehdi Amini" <<a href="mailto:mehdi.amini@apple.com" target="_blank">mehdi.amini@apple.com</a>><br>
> Cc: "llvm-dev" <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>>, "Hal Finkel" <<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>>, "Quentin Colombet" <<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>><br>
> Sent: Thursday, July 28, 2016 2:59:02 PM<br>
> Subject: Re: A thought to improve IPRA<br>
><br>
><br>
> I have been working on PGO driven IPRA and I want to measure if this<br>
> help to reduce execution time. So as mentioned earlier the idea is<br>
> to make cold function register usage free i.e saving and restoring<br>
> all used register by such cold function so caller of that function<br>
> will have more free registers. So here I am changing standard callee<br>
> saved registers set to a set which will be decided dynamically based<br>
> on the actual register usage.<br>
><br>
> I am facing few problems to get this working:<br>
> 1 ) While generating CFI for such function it requires to map Dwarf<br>
> register to LLVM register and even if we force LLVM to use Dwarf<br>
> register number for CFI then also it will be wrong for some register<br>
> for which currently we don't have such mapping for example R8D<br>
> register on X86 (when dealing with actual register usage info we may<br>
> have such case where R8D is being used)<br>
> To fix this I tried to filter the functions which will be optimized<br>
> by putting a constraints that it should have attribute NoUnwind but<br>
> that does not help. Is it possible to disable CFI generation?<br>
<br>
</span>Disabling CFI generation does not seem like the right solution. If the R8D definition, and similar, need DWARF register numbers, then we should fix that (you can try rearranging things and using DwarfRegAlias, or at least for testing, add the same DwarfRegNum as for R8).<br>
<span>Adding DwarfRegNum as for R8 does not work because the mapping is currently generated as a sorted array on the first value of the key for DwarfLLVMRegPair. So in the build directory in file X86GenRegisterInfo.inc this will add 2 different entries for mapping LLVM Reg to Dwarf number i.e R8 -> 8 and R8D -> 8 but in the array of mapping Dwarf to LLVM Reg there is only entry as it will add 8 only once. </span> </blockquote><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;"><span>
><br>
><br>
> 2) R8D is a 48 bit register<br>
<br>
</span>Why do you say that? For one thing, it is in a register class GR32 and holds only 32-bit values.<br></blockquote><div id="DWT343">Sorry this is my bad R8D is 32 bit value. To get this working changing CC for cold functions to "preserve_all" seems to be easy and safe way. Let me know your thought about this.</div></div></div></div></blockquote>Sounds like a reasonable thing to try.<br><br> -Hal<br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><div></div><div><br></div><div>-Vivek</div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<br>
-Hal<br>
<div><div><br>
> but pushing and popping such register is<br>
> not allowed and current implementation for CalleeSaved Register also<br>
> uses either 64 bit or 32 bit version of X86 instruction according to<br>
> target. So here I think it may be good to push/pop R8 for R8D (i.e I<br>
> don't want to change current implementation which inserts MI for<br>
> CSR) for that I need to find biggest register for which given<br>
> register is alias like R8 has R8D as alias. How can I find that?<br>
> I tried to use getMatchingSuperReg(unsigned Reg, unsigned SubIdx,<br>
> const TargetRegisterClass *RC) but here I don't know what will be<br>
> SubIdx for given Reg in given RC.<br>
><br>
><br>
> So for example if a function which should be optimized for above<br>
> optimization is having following set of clobbered registers:<br>
> R8D,R8, ECX, EAX, RAX, ESI It should push/pop R8, RCX, RAX, RSI.<br>
><br>
><br>
> Please help!<br>
> - Vivek<br>
><br>
><br>
><br>
><br>
> On Sat, Jul 9, 2016 at 12:26 AM, vivek pandya <<br>
> <a href="mailto:vivekvpandya@gmail.com" target="_blank">vivekvpandya@gmail.com</a> > wrote:<br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
> On Sat, Jul 9, 2016 at 12:18 AM, Mehdi Amini < <a href="mailto:mehdi.amini@apple.com" target="_blank">mehdi.amini@apple.com</a><br>
> > wrote:<br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
> On Jul 8, 2016, at 11:41 AM, vivek pandya < <a href="mailto:vivekvpandya@gmail.com" target="_blank">vivekvpandya@gmail.com</a> ><br>
> wrote:<br>
><br>
><br>
><br>
><br>
> On Fri, Jul 8, 2016 at 11:46 PM, Mehdi Amini < <a href="mailto:mehdi.amini@apple.com" target="_blank">mehdi.amini@apple.com</a><br>
> > wrote:<br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
> On Jul 8, 2016, at 11:12 AM, vivek pandya < <a href="mailto:vivekvpandya@gmail.com" target="_blank">vivekvpandya@gmail.com</a> ><br>
> wrote:<br>
><br>
><br>
><br>
><br>
><br>
> Hello LLVM Developers,<br>
><br>
><br>
> I have a thought to improve IPRA and I would like summaries<br>
> discussion on IRC regarding that so we can develop an idea out of<br>
> that if it really helps.<br>
><br>
><br>
> So idea is to have more callee saved registers at infrequently called<br>
> leaf procedures and try provide more registers to procedures which<br>
> are in upper region of the call graph. But as pointed out by Quentin<br>
> this optimization may help in context of "true" IPRA but in our case<br>
> we may not require this. But I think that it can improve performance<br>
> in current IPRA. I explain both arguments ( Quentin's and mine) with<br>
> following example.<br>
><br>
><br>
> Consider following call sequence A->B->C , here C is very less time<br>
> called leaf procedure while A is called frequently and B may call C<br>
> based on some condition now while propagating actual register usage<br>
> information from C to A we almost clobbered most of the registers so<br>
> in this case as per Quentin's point we does not hurt the performance<br>
> as we fall back to CC but I think we can improve the performance as<br>
> follows:<br>
> If we mark every register preserved by C (i.e having more spill<br>
> reloads at procedure entry and exit ) and if this can help at A.<br>
> Suppose A requires more number of distinct registers than CC can<br>
> provide and if not provided it will spill variables to memory. Now<br>
> if we can provide more registers at A by having more spills at C<br>
> then we can save spill at A which can be beneficial because A is<br>
> frequently called but C is less frequently called and thus reducing<br>
> total number of spill/restore in program execution.<br>
><br>
><br>
> However again effect of this optimization will be limited by the<br>
> scope of current IPRA (i.e one Module only) because we can' really<br>
> propagate the details about more callee saved registers to caller<br>
> which is defined in other module, but still it may helpful.<br>
><br>
><br>
> Any thoughts on this ?<br>
><br>
><br>
><br>
><br>
> I think it is interesting, have you considered:<br>
><br>
><br>
> - the code size impact? (C will have a lot of spills)<br>
> Yes, this needs to be address with some heuristics based on call<br>
> frequency to C and no of clobbers it has. Also can we say that a<br>
> function which does not have any kind of call instruction in it's<br>
> body will have less clobbers ?<br>
><br>
><br>
> I am not sure what you mean.<br>
> A function which may do lots of computation but does not required to<br>
> call any other function may not have too many simultaneous live<br>
> ranges thus with very few registers it can be compiled.<br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
> - what if C is cold but all (most) of its call sites are located in<br>
> different modules?<br>
> Can we user Uses to get no of call site in current module and based<br>
> on that we decide to optimize? Again some heuristics .<br>
><br>
><br>
> Of course, but what I’m mentioning is exactly what does not work with<br>
> that.<br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
><br>
> - an alternative approach where we would break the CGSCC ordering to<br>
> codegen B and A before C, so we would be able to spill minimally<br>
> when performing the codegen for C?<br>
> Do you here mean marking all preserve for C while code gen for B and<br>
> then when we come to C (top-down) we may avoid some spills if C can<br>
> use regs which are not really used by B?<br>
><br>
><br>
> Yes, but it may be harder to implement for not much gain after all.<br>
><br>
><br>
><br>
><br>
><br>
> Also this can be applied to a function which is less frequently<br>
> called and which may not be a leaf function. It may help.<br>
><br>
><br>
> Sure, you can just refer to this as “PGO driven IPRA”.<br>
> Ok I will look into this.<br>
><br>
><br>
> Vivek<br>
><br>
><br>
><br>
><br>
><br>
> —<br>
> Mehdi<br>
><br>
><br>
><br>
><br>
<br>
</div></div><span><font color="#888888">--<br>
Hal Finkel<br>
Assistant Computational Scientist<br>
Leadership Computing Facility<br>
Argonne National Laboratory<br>
</font></span></blockquote></div><br></div></div>
</blockquote><br><br><br>-- <br><div><span name="x"></span>Hal Finkel<br>Assistant Computational Scientist<br>Leadership Computing Facility<br>Argonne National Laboratory<span name="x"></span><br></div></div></body></html>