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<div class="moz-cite-prefix">Dear Raul,<br>
<br>
Instruction selection and instruction scheduling is, to the best
of my knowledge, done at the MachineInstr (MI) IR level. The
documentation you've read is on the target independent LLVM IR.<br>
<br>
You will probably need to read the documentation on LLVM's code
generator. The documents on Writing an LLVM Backend, the LLVM
Target Independent Code Generator, and Machine IR Format Reference
Manual is probably what you need to read if you want to work with
the SelectionDAG and the machine code that is generated by LLVM
during code generation.<br>
<br>
If you just want to analyze LLVM IR, then all the virtual register
values are in SSA form and therefore have explicit def-use chains
over which you can iterate (see the LLVM Programmer's Guide). If
you want a DAG for memory dependencies, then you should send a
follow-up email to the list as that is its own whole topic.<br>
<br>
Regards,<br>
<br>
John Criswell<br>
<br>
On 6/27/16 10:03 AM, Raul Garcia via llvm-dev wrote:<br>
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<div>Hello All,<br>
<br>
I would like your help to learn how to traverse an LLVM DAG and
perform some analysis. I know that llc can be used to view a
DAG, but I would like to manipulate them. In particular I'm
interested in the instruction selection and the scheduling DAGs.
<br>
<br>
I have read the documentation about writing an analysis pass and
I know how to traverse a basic block on a LLVM IR assembly file,
but I don't know how to do the same for a scheduled DAG.<br>
<br>
Could you tell me:<br>
<br>
-How are the DAGs generated? Where is the source code that
implement this functionality?<br>
-Is there an example to traverse a DAG with selected/scheduled
instructions?<br>
<br>
<br>
Regards,<br>
Raul. <br>
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<br>
<p><br>
</p>
<pre class="moz-signature" cols="72">--
John Criswell
Assistant Professor
Department of Computer Science, University of Rochester
<a class="moz-txt-link-freetext" href="http://www.cs.rochester.edu/u/criswell">http://www.cs.rochester.edu/u/criswell</a></pre>
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