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please see comments below
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<div class="">On Jun 27, 2016, at 23:36, John Criswell via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div>
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<div class="moz-cite-prefix">Dear Raul,<br class="">
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Instruction selection and instruction scheduling is, to the best of my knowledge, done at the MachineInstr (MI) IR level. The documentation you've read is on the target independent LLVM IR.<br class="">
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<div>Instruction selection is done on SelectionDAG, which is build from LLVM IR. After instruction selection, target-independent IR is turned into</div>
<div>machine instructions (MI). At this time, MI is still in SSA form. Then LLVM backend do PHI elimination, then machine instruction scheduling.</div>
<div>LLVM uses a list scheduler to perform both pre-RA and post-RA scheduling.</div>
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You will probably need to read the documentation on LLVM's code generator. The documents on Writing an LLVM Backend, the LLVM Target Independent Code Generator, and Machine IR Format Reference Manual is probably what you need to read if you want to work with
the SelectionDAG and the machine code that is generated by LLVM during code generation.<br class="">
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If you just want to analyze LLVM IR, then all the virtual register values are in SSA form and therefore have explicit def-use chains over which you can iterate (see the LLVM Programmer's Guide). If you want a DAG for memory dependencies, then you should send
a follow-up email to the list as that is its own whole topic.<br class="">
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John Criswell<br class="">
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On 6/27/16 10:03 AM, Raul Garcia via llvm-dev wrote:<br class="">
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<div class="">Hello All,<br class="">
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I would like your help to learn how to traverse an LLVM DAG and perform some analysis. I know that llc can be used to view a DAG, but I would like to manipulate them. In particular I'm interested in the instruction selection and the scheduling DAGs.
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<div>I’m not familiar with instruction selection. Schedule DAG is build from machine instructions. see class ScheduleDAG and its subclasses ScheduleDAGInstrs, ScheduleDAGMI, ScheduleDAGMIList. The building of schedule DAG is done in ScheduleDAGInstrs::buildSchedGraph.</div>
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<div>see class MachineScheduler defines the list scheduler. MachineScheduler use an instance of ScheduleDAGInstrs to schedule machine instructions.</div>
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I have read the documentation about writing an analysis pass and I know how to traverse a basic block on a LLVM IR assembly file, but I don't know how to do the same for a scheduled DAG.<br class="">
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Could you tell me:<br class="">
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-How are the DAGs generated? Where is the source code that implement this functionality?<br class="">
-Is there an example to traverse a DAG with selected/scheduled instructions?<br class="">
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Regards,<br class="">
Raul. <br class="">
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<pre class="moz-signature" cols="72">--
John Criswell
Assistant Professor
Department of Computer Science, University of Rochester
<a class="moz-txt-link-freetext" href="http://www.cs.rochester.edu/u/criswell">http://www.cs.rochester.edu/u/criswell</a></pre>
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