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<div>ok，got it！thanks！<br>
<br>
发自我的 iPhone</div>
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在 2016年5月13日，15:37，James Molloy <<a href="mailto:james@jamesmolloy.co.uk">james@jamesmolloy.co.uk</a>> 写道：<br>
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<div dir="ltr">Hi Xing,
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<div>Most of what you said was correct, up until the end! :</div>
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<p style="color:rgb(0,0,0);font-family:calibri,arial,helvetica,sans-serif;font-size:16px;line-height:24px">
> In this code, an 128bit ASIMD FP multiply accumulate(FMLA/FMLS Q-form) requires two `A57UnitV`s, meaning that two clock cycles are needed.</p>
<p style="color:rgb(0,0,0);font-family:calibri,arial,helvetica,sans-serif;font-size:16px;line-height:24px">
The ProcResGroup is an "OR" relationship, not an "AND". It says that a V op can go to EITHER the W or X pipes, not both. So a 128-bit FP op is modelled as having two V ops, which could either be [W, X] (simultaneously), [W, W] (requiring two cycles), or [X,
X] (requiring two cycles).</p>
<p style="color:rgb(0,0,0);font-family:calibri,arial,helvetica,sans-serif;font-size:16px;line-height:24px">
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</p>
<p style="color:rgb(0,0,0);font-family:calibri,arial,helvetica,sans-serif;font-size:16px;line-height:24px">
Cheers,</p>
<p style="color:rgb(0,0,0);font-family:calibri,arial,helvetica,sans-serif;font-size:16px;line-height:24px">
James</p>
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<div dir="ltr">On Fri, 13 May 2016 at 01:13 Xing Su via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> wrote:<br>
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<p><span style="font-size:12pt">Hello everybody,</span><br>
</p>
<p><br>
</p>
<p>I'm reading the .td files defining the Cortex-A57 processor,</p>
<p>which is a subtarget of AArch64 target, and there is something</p>
<p>confusing me in the `AArch64SchedA57.td` file.</p>
<p><br>
</p>
<p>In the top of `AArch64SchedA57.td`, various processor resource are</p>
<p>defined, as follows</p>
<p><br>
</p>
<p>```</p>
<p>def A57UnitB : ProcResource<1>; // Type B micro-ops</p>
<p>def A57UnitI : ProcResource<2>; // Type I micro-ops</p>
<p>def A57UnitM : ProcResource<1>; // Type M micro-ops</p>
<p>def A57UnitL : ProcResource<1>; // Type L micro-ops</p>
<p>def A57UnitS : ProcResource<1>; // Type S micro-ops</p>
<p>def A57UnitX : ProcResource<1>; // Type X micro-ops</p>
<p>def A57UnitW : ProcResource<1>; // Type W micro-ops</p>
<p>let SchedModel = CortexA57Model in {</p>
<p> def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops</p>
<p>}</p>
<p>```</p>
<p><br>
</p>
<p>According the Cortex-A57 software optimization manual, Cortex-A57 has 8</p>
<p>function units in the backend,</p>
<p><br>
</p>
<p>- Branch(B)</p>
<p>- Integer 0(I0)</p>
<p>- Integer 1(I1)</p>
<p>- Integer Muti-Cycle(M)</p>
<p>- Load(L)</p>
<p>- Store(S)</p>
<p>- FP/ASIMD 0(F0)</p>
<p>- FP/ASIMD 1(F1)</p>
<p><br>
</p>
<p>So I think `A57UnitW` and `A57UnitX` should be the TableGen records</p>
<p>defining pipeline F0 and F1, respectively. So `A57UnitW` and `A57UnitX`</p>
<p>together compose a `ProcResGroup`, `A57UnitV`,</p>
<p>which can execute a 128bit ASIMD floating point operation,</p>
<p>such as FMLA(Q-form), in a single clock cycle.</p>
<p>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^</p>
<p><br>
</p>
<p>But in line 479-483 of `AArch64SchedA57.td`, as shown below</p>
<p><br>
</p>
<p>```</p>
<p>def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; }</p>
<p>def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; }</p>
<p>def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>;</p>
<p>def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;</p>
<p>def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;</p>
<p>```</p>
<p><br>
</p>
<p>In this code, an 128bit ASIMD FP multiply accumulate(FMLA/FMLS Q-form) requires</p>
<p>two `A57UnitV`s, meaning that two clock cycles are needed.</p>
<p>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^</p>
<p><br>
</p>
<p>There must be something wrong with my understanding, anyone could help me</p>
<p>figure out the problem? thanks a lot!</p>
<p><br>
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<p><br>
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<p><br>
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<p>Xing</p>
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