<div dir="ltr"><div>Christoff,<br><br></div>Thanks for the reply. Comments below:<br><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Apr 26, 2016 at 5:09 AM, Christof Douma <span dir="ltr"><<a href="mailto:Christof.Douma@arm.com" target="_blank">Christof.Douma@arm.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<div>Hi Phil.</div>
<div><br>
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<div>You more or less answered your own question, but let me give you some more info. Maybe it is of use.</div>
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<div>From what I understand the <span style="font-size:13px">SchedMachineModel </span>is the future, although it is not as powerful as itineraries at present. The mi-scheduler is mostly developed around out-of-orders cores, I believe (I love to hear arguments
on the contrary). Some of the constraints that can be found in in-order micro architectures cannot be expressed in the per-operand scheduling model and the heuristics of the pre-RA scheduling pass is probably a bit too focussed on register pressure for in-order
cores (I have no numbers, just hearsay). </div>
<div><br>
</div>
<div>There is some documentation in comments at the start of include/llvm/Target/TargetSchedule.td that you might find useful. If you are going to look at an existing scheduling model, I suggest to look at an in-order core. A good example would be AArch64/AArch64SchedA53.td.
If itineraries are present, they are used by the mi-scheduler next to the SchedMachineModel to detect hazards. I think that is the only place where the mi-scheduler uses itineraries.</div>
<div><br></div></div></blockquote><div><br></div><div>If I don't use the mi-scheduler (since we already have itineraries defined for most ops and this is an in-order processor so it sounds like I wouldn't get much benefit from using the mi-scheduler), how can I tell if my itinerary definitions are being used? Is there any way to get a report or debug info?<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word;font-size:14px;font-family:Calibri,sans-serif;color:rgb(0,0,0)"><div>
</div>
<div>There are some magic numbers you need for in-order operation. Most notably MicroOpBufferSize should be set to 0 for full in-order behaviour. You also want to set CompleteModel to 0 as that prevents asserts due to instructions without scheduling information.
There is a script that might help you to visualise if you have provided scheduling information in the <span style="font-size:13px">SchedMachineModel </span>for all instructions (utils/schedcover.py). </div></div></blockquote><div><br></div><div>I do not see schedcover.py in my LLVM source tree, but we're still on LLVM 3.6 so this could be the issue. Are there other ways to debug itineraries?<br> <br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word;font-size:14px;font-family:Calibri,sans-serif;color:rgb(0,0,0)"><div>It is very simplistic and takes as input the debug output
of tablegen. There are some usage comments at the beginning.</div>
<div><br>
</div>
<div>Regards,</div>
<div>Christof</div>
<div><br>
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<span style="font-weight:bold">From: </span>llvm-dev <<a href="mailto:llvm-dev-bounces@lists.llvm.org" target="_blank">llvm-dev-bounces@lists.llvm.org</a>> on behalf of Phil Tomson via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><br>
<span style="font-weight:bold">Reply-To: </span>Phil Tomson <<a href="mailto:phil.a.tomson@gmail.com" target="_blank">phil.a.tomson@gmail.com</a>><br>
<span style="font-weight:bold">Date: </span>Wednesday, 20 April 2016 23:06<span class=""><br>
<span style="font-weight:bold">To: </span>LLVM Developers Mailing List <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><br>
</span><span style="font-weight:bold">Subject: </span>Re: [llvm-dev] How to get started with instruction scheduling? Advice needed.<br>
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<div><br>
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<div dir="ltr">
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<div>I notice from looking at ARMScheduleA9.td that there seems to be a hybrid approach where they still have itineraries but also use SchedMachineModel:<br>
<br>
// ===---------------------------------------------------------------------===//<br>
// The following definitions describe the simpler per-operand machine model.<br>
// This works with MachineScheduler and will eventually replace itineraries.<br>
<br>
class A9WriteLMOpsListType<list<WriteSequence> writes> {<br>
list <WriteSequence> Writes = writes;<br>
SchedMachineModel SchedModel = ?;<br>
}<br>
<br>
// Cortex-A9 machine model for scheduling and other instruction cost heuristics.<br>
def CortexA9Model : SchedMachineModel {<br>
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.<br>
let MicroOpBufferSize = 56; // Based on available renamed registers.<br>
let LoadLatency = 2; // Optimistic load latency assuming bypass.<br>
// This is overriden by OperandCycles if the<br>
// Itineraries are queried instead.<br>
let MispredictPenalty = 8; // Based on estimate of pipeline depth.<br>
<br>
let Itineraries = CortexA9Itineraries;<br>
<br>
// FIXME: Many vector operations were never given an itinerary. We<br>
// haven't mapped these to the new model either.<br>
let CompleteModel = 0;<br>
}<br>
<br>
</div>
I'm guessing this is probably the way forward for my case since Itineraries seem to be already mostly defined.<br>
<br>
</div>
Phil<br>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Wed, Apr 20, 2016 at 1:27 PM, Phil Tomson <span dir="ltr">
<<a href="mailto:phil.a.tomson@gmail.com" target="_blank">phil.a.tomson@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div dir="ltr">
<div>So if I use the <font size="2">SchedMachineModel method, can I just skip itineraries?<span><font color="#888888"><br>
<br>
</font></span></font></div>
<span><font color="#888888"><font size="2">Phil<br>
</font></font></span></div>
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<div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <span dir="ltr">
<<a href="mailto:slarin@codeaurora.org" target="_blank">slarin@codeaurora.org</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">Target does make a difference. VLIW needs more hand-holding. For what you are describing it should be fairly simple.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">Best strategy – see what other targets do. ARM might be a good start for generic superscalar. Hexagon for VLIW style scheduling.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">Depending on what you decide, you might need different target hooks.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">Sergei<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:10.5pt;font-family:Consolas;color:#1f497d">---<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:10.5pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation</span><span style="font-size:10.5pt;font-family:Consolas;color:#1f497d"><u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u> <u></u></span></p>
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<p class="MsoNormal"><b><span style="font-size:11pt;font-family:Calibri,sans-serif">From:</span></b><span style="font-size:11pt;font-family:Calibri,sans-serif"> llvm-dev [mailto:<a href="mailto:llvm-dev-bounces@lists.llvm.org" target="_blank">llvm-dev-bounces@lists.llvm.org</a>]
<b>On Behalf Of </b>Phil Tomson via llvm-dev<br>
<b>Sent:</b> Wednesday, April 20, 2016 12:51 PM<br>
<b>To:</b> LLVM Developers Mailing List <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><br>
<b>Subject:</b> [llvm-dev] How to get started with instruction scheduling? Advice needed.<u></u><u></u></span></p>
</div>
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<div>
<p class="MsoNormal"><u></u> <u></u></p>
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<div>
<p class="MsoNormal">I need to add instruction scheduling for a new target which is a fairly simple in-order execution machine.<br>
<br>
I've been watching this presentation from a 2014 LLVM dev meeting as it seems relevant:<u></u><u></u></p>
</div>
<p class="MsoNormal" style="margin-bottom:12.0pt">"SchedMachineModel: Adding and Optimizing a Subtarget"
<a href="http://llvm.org/devmtg/2014-10/Slides/Estes-MISchedulerTutorial.pdf" target="_blank">
http://llvm.org/devmtg/2014-10/Slides/Estes-MISchedulerTutorial.pdf</a><u></u><u></u></p>
</div>
<p class="MsoNormal" style="margin-bottom:12.0pt">In this presentation the author says that there have been several ways to approach scheduling in LLVM over the years:<u></u><u></u></p>
<ul type="disc">
<li class="MsoNormal"><span style="font-size:10.0pt">Pre 2008: SelectionDAGISel pass creates the ScheduleDAG from the SelectionDAG at the end of instruction selection</span><u></u><u></u></li><li class="MsoNormal"><span style="font-size:10.0pt">ScheduleDAG works on SelectionDAG Nodes (SDNodes)</span><u></u><u></u></li><li class="MsoNormal"><span style="font-size:10.0pt">Circa 2008: Post Register </span>
<u></u><u></u></li></ul>
<div>
<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10pt;font-family:Arial,sans-serif">Allocation pass added for
</span><span style="font-family:Arial,sans-serif"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10pt;font-family:Arial,sans-serif">instruction selection ( SchedulePostRATDList
</span><span style="font-family:Arial,sans-serif"><u></u><u></u></span></p>
<div>
<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10pt;font-family:Arial,sans-serif">works on MachineInstrs)</span><span style="font-family:Arial,sans-serif"><u></u><u></u></span></p>
</div>
</div>
<ul type="disc">
<li class="MsoNormal"><span style="font-size:10.0pt">Circa 2012: MIScheduler </span>
<u></u><u></u></li></ul>
<div>
<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10pt;font-family:Arial,sans-serif">(ScheduleDAGMI) added as
</span><span style="font-family:Arial,sans-serif"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10pt;font-family:Arial,sans-serif">separate pass for pre-RA
</span><span style="font-family:Arial,sans-serif"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10pt;font-family:Arial,sans-serif">scheduling</span><span style="font-family:Arial,sans-serif"><u></u><u></u></span></p>
</div>
<ul type="disc">
<li class="MsoNormal"><span style="font-size:10.0pt">Circa 2014: MIScheduler </span>
<u></u><u></u></li></ul>
<div>
<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10pt;font-family:Arial,sans-serif">adapted to optionally replace
</span><span style="font-family:Arial,sans-serif"><u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10pt;font-family:Arial,sans-serif">PostRA Scheduler</span><span style="font-family:Arial,sans-serif"><u></u><u></u></span></p>
</div>
<p><span style="font-size:10.0pt">In the presentation he goes with defining a subclass of SchedMachineModel</span> in the schedule .td file. And apparently with this approach there are no instruction itineraries.<u></u><u></u></p>
<p>So I'm wondering: what's the current recommended way to approach this and does it depend on the type or target? (in-order, superscalar, out of order, VLIW...)?<u></u><u></u></p>
<p>Someone earlier started to define instruction itineraries for our target. Should I continue down this road or move over to the SchedMachineModel approach? Are there other recommended presentations/documents that I should be looking at?<u></u><u></u></p>
<p><u></u> <u></u></p>
<p>Thanks.<u></u><u></u></p>
<p>Phil<u></u><u></u></p>
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