<html><head><style type='text/css'>p { margin: 0; }</style></head><body><div style='font-family: arial,helvetica,sans-serif; font-size: 10pt; color: #000000'><br><hr id="zwchr"><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><b>From: </b>"Семен Колтон" <samkolton@gmail.com><br><b>To: </b>"Hal Finkel" <hfinkel@anl.gov><br><b>Cc: </b>"via llvm-dev" <llvm-dev@lists.llvm.org><br><b>Sent: </b>Friday, April 8, 2016 6:38:22 AM<br><b>Subject: </b>Re: [llvm-dev] Inline asm clobber registers name<br><br><div dir="ltr"><p class="MsoNormal">Hi Hal,</p>
<p class="MsoNormal"><br></p><p class="MsoNormal">In that case I will start implementing it in core LLVM. What
I want to do is add table with AsmNames to TargetGenRegisterInfo.inc similar to
RegStrings table. This table could be used by getRegForInlineAsmConstraint. </p>
<p class="MsoNormal">I don’t want to force all back-ends to use AsmNames instead
of def-names. There is useful review for
this created by Tom Stellard: <a href="http://reviews.llvm.org/D15614" target="_blank">http://reviews.llvm.org/D15614</a>.</p>
<p id="DWT2771" class="MsoNormal">What do you think about all this?</p></div></blockquote>I think this sounds reasonable. I'll look at Tom's patch.<br><br> -Hal<br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><div dir="ltr"><p class="MsoNormal"></p>
<p class="MsoNormal">Thanks,</p>
<p class="MsoNormal">Sam</p><div class="gmail_extra"><br><div class="gmail_quote">2016-04-07 18:46 GMT+03:00 Hal Finkel <span dir="ltr"><<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>></span>:<br><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;"><div><div style="font-family: arial,helvetica,sans-serif; font-size: 10pt; color: rgb(0, 0, 0);"><br><br><hr><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><b>From: </b>"Семен Колтон via llvm-dev" <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><br><b>To: </b>"via llvm-dev" <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><br><b>Sent: </b>Thursday, April 7, 2016 10:06:21 AM<br><b>Subject: </b>[llvm-dev] Inline asm clobber registers name<span class=""><br><br><div dir="ltr"><div><p class="MsoNormal">Hi all,</p>
<p class="MsoNormal"><br></p><p class="MsoNormal">I am currently working on AMDGPU inline assembly and
encountered problem with naming clobber registers in asm constraints. It looks
like by default LLVM tries to match register specified in constraint to
register name of register definition in .td file but not to the AsmName for
this register.</p>
<p class="MsoNormal"><br></p><p class="MsoNormal">For example if we have register definition:</p>
<p class="MsoNormal" style="text-indent: 36pt;"><span style="font-size: 9pt; line-height: 115%; font-family: Consolas; color: black;">def MYReg0 : Register<"r0", 0>;</span></p>
<p class="MsoNormal">We want to create inline assembly and add this register to
clobbers list. Inline assembly should look something like this:</p>
<p class="MsoNormal"> <span style="font-size: 9pt; line-height: 115%; font-family: Consolas;">i32 asm "nop", "~{r0}" ()</span></p>
<p class="MsoNormal"><br></p><p class="MsoNormal">We used AsmName
for register MYReg0 inside clobbers list. But this constraint fails to work
because <span style="font-size: 10pt; line-height: 115%; font-family: 'Segoe UI',sans-serif; color: black;">TargetLowering::getRegForInlineAsmConstraint()</span>
tries to match register definition name (“MYReg0”) not its AsmName (“r0”). So
to make this work we should write this assembly:</p>
<p class="MsoNormal"> <span style="font-size: 9pt; line-height: 115%; font-family: Consolas;">i32 asm "nop", "~{MYReg0}" ()</span></p>
<p class="MsoNormal"><br></p><p class="MsoNormal">I believe that
this behavior is not correct. It works because in most back-ends register
definition names and AsmNames are equal (<span style="font-size: 10pt; line-height: 115%; font-family: 'Segoe UI',sans-serif; color: black;">e.g. def EAX : X86Reg<"eax", ...></span>) but in AMDGPU we want to have different
def-names and AsmNames.</p>
<p class="MsoNormal"><br></p><p class="MsoNormal">This might be done
by changing core LLVM code or in target-specific <span style="font-size: 10pt; line-height: 115%; font-family: 'Segoe UI',sans-serif; color: black;">getRegForInlineAsmConstraint() method. What do you suppose to
be better solution?</span></p></div></div></span></blockquote>I agree. I have the following FIXME in PPCISelLowering:<br><br> // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers<br> // (which we call X[0-9]+). If a 64-bit value has been requested, and a<br> // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent<br> // register.<br> // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use<br> // the AsmName field from *RegisterInfo.td, then this would not be necessary.<br> if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&<br> PPC::GPRCRegClass.contains(R.first))<br> return std::make_pair(TRI->getMatchingSuperReg(R.first,<br> PPC::sub_32, &PPC::G8RCRegClass),<br> &PPC::G8RCRegClass);<br><br> -Hal<br><br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><div dir="ltr"><div><p class="MsoNormal"><span style="font-size: 10pt; line-height: 115%; font-family: 'Segoe UI',sans-serif; color: black;"></span></p><p class="MsoNormal"><span style="font-size: 10pt; line-height: 115%; font-family: 'Segoe UI',sans-serif; color: black;"><br></span></p>
<p class="MsoNormal"><span style="font-size: 10pt; line-height: 115%; font-family: 'Segoe UI',sans-serif; color: black;">Thanks,</span></p>
<p class="MsoNormal"><span style="font-size: 10pt; line-height: 115%; font-family: 'Segoe UI',sans-serif; color: black;">Sam</span></p></div>
</div>
<br>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</a><span class="HOEnZb"><font color="#888888"><br></font></span></blockquote><span class="HOEnZb"><font color="#888888"><br><br><br>-- <br><div><span></span>Hal Finkel<br>Assistant Computational Scientist<br>Leadership Computing Facility<br>Argonne National Laboratory<span></span><br></div></font></span></div></div></blockquote></div><div class="gmail_signature"><br></div>
</div></div>
</blockquote><br><br><br>-- <br><div><span name="x"></span>Hal Finkel<br>Assistant Computational Scientist<br>Leadership Computing Facility<br>Argonne National Laboratory<span name="x"></span><br></div></div></body></html>