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    <div class="moz-cite-prefix">On 2/18/16 1:17 PM, Laura personen
      wrote:<br>
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              <div>Thank you for your swift reply.<br>
                <br>
              </div>
              I also need some reference about instruction sequence in
              llvm. I mean, do the order of instructions remain the same
              as they appear in a .ll file? or do they change by
              different optimizations (e.g. <a moz-do-not-send="true"
                class=""
href="http://llvm.org/docs/CodeGenerator.html#ssa-based-machine-code-optimizations">SSA-based
                Machine Code Optimizations</a>, <a
                moz-do-not-send="true" class=""
href="http://llvm.org/docs/CodeGenerator.html#late-machine-code-optimizations">Late
                Machine Code Optimizations</a>, etc.)? <br>
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    <br>
    I believe there are optimizations that can change the order of
    instructions at the LLVM IR level.  You can find a list of LLVM
    optimizations at <a class="moz-txt-link-freetext" href="http://llvm.org/docs/Passes.html">http://llvm.org/docs/Passes.html</a>.<br>
    <br>
    When generating native code, the Instruction Scheduler will reorder
    the native code instructions as well.<br>
    <br>
    <blockquote
cite="mid:CAMW9UP8Af=C8QE_n1rQRcOpyv6pRB+eBOnft9XwLnOTcFCmriA@mail.gmail.com"
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              If they change, which algorithms are used for reordering
              instructions? I appreciate a reference that explains them
              or just gives the name of the algorithms that are used.<br>
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    <br>
    You can look at the list of passes, but to get more detail, you will
    probably need to examine the source code.<br>
    <br>
    Regards,<br>
    <br>
    John Criswell<br>
    <br>
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cite="mid:CAMW9UP8Af=C8QE_n1rQRcOpyv6pRB+eBOnft9XwLnOTcFCmriA@mail.gmail.com"
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          BR<br>
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        Laura<br>
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      <div class="gmail_extra"><br>
        <div class="gmail_quote">On Thu, Feb 18, 2016 at 6:45 PM, John
          Criswell <span dir="ltr"><<a moz-do-not-send="true"
              href="mailto:jtcriswel@gmail.com" target="_blank">jtcriswel@gmail.com</a>></span>
          wrote:<br>
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            <div><span class="">
                <div>On 2/18/16 12:03 PM, Laura personen via llvm-dev
                  wrote:<br>
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                        <div>Hi,<br>
                          <br>
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                        Is there any way to detect which virtual
                        registers are assigned to physical registers and
                        which ones are assigned to memory slots?<br>
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                <br>
              </span> At the LLVM IR level, no.  However, it might be
              possible for a MachineFunctionPass to determine this or to
              modify the register allocator to record this information
              somewhere for query by a MachineFunctionPass later.<br>
              <br>
              Regards,<br>
              <br>
              John Criswell<br>
              <br>
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                    BR<br>
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                  Laura<br>
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                <br>
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                <span class="HOEnZb"> </span></blockquote>
              <span class="HOEnZb"> <br>
                <br>
                <pre cols="72">-- 
John Criswell
Assistant Professor
Department of Computer Science, University of Rochester
<a moz-do-not-send="true" href="http://www.cs.rochester.edu/u/criswell" target="_blank">http://www.cs.rochester.edu/u/criswell</a></pre>
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    <pre class="moz-signature" cols="72">-- 
John Criswell
Assistant Professor
Department of Computer Science, University of Rochester
<a class="moz-txt-link-freetext" href="http://www.cs.rochester.edu/u/criswell">http://www.cs.rochester.edu/u/criswell</a></pre>
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