<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">I never thought I’d see the day when someone proposed treating the 6502 like a GPU…<div class=""><br class=""></div><div class="">—escha</div><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Feb 12, 2016, at 6:30 AM, Bruce Hoult via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">I think it would be sufficient to pick 8 or 16 pairs of zero page locations as the "registers". Who needs 128 registers, unless you're also doing inter-procedural register allocation? True, that would be a good idea, so non-recursive functions can be allocated a fixed set of registers (based on the maximum call depth they are used from?) and never need to save/restore anything. That would be useful for other CPUs too. but LLVM doesn't support this.<div class=""><br class=""></div><div class="">As for treating 1-2 as a register as well as 0-1 and 2-3? Theoretically possible, of course, but needless complexity.</div></div><div class="gmail_extra"><br class=""><div class="gmail_quote">On Fri, Feb 12, 2016 at 4:54 PM, Krzysztof Parzyszek via llvm-dev <span dir="ltr" class=""><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank" class="">llvm-dev@lists.llvm.org</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On 2/12/2016 7:23 AM, Bruce Hoult via llvm-dev wrote:<br class="">
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
I haven't seen what you are doing, but if I was writing a back end for<br class="">
the 6502, I'd lie to LLVM and describe RAM page 0 as being the real<br class="">
registers, and A, X and Y as being special purpose registers used for<br class="">
temporaries.<br class="">
</blockquote>
<br class=""></span>
How did you get the "(z), x" and "(z, y)" addressing modes to work with this scheme? The "z" is two adjacent zero-page bytes---did you model 16-bit registers as all possible pairs of adjacent 0p addresses?<br class="">
<br class="">
-Krzysztof<span class="HOEnZb"><font color="#888888" class=""><br class="">
<br class="">
-- <br class="">
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation</font></span><div class="HOEnZb"><div class="h5"><br class="">
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