<div dir="ltr">Thanks, Igor and Elena!<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jan 25, 2016 at 4:28 AM, Breger, Igor <span dir="ltr"><<a href="mailto:igor.breger@intel.com" target="_blank">igor.breger@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Hello,<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";background:white">Enabling vector masked_load/store to AVX1 using
<span> </span>AVX1 FP instructions (vmaskmovps/pd) in place of the AVX2 int instructions (vpmaskmovd/q)
<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";background:white">committed to r258675.
<span style="color:black">(<a href="http://reviews.llvm.org/D16528" target="_blank">http://reviews.llvm.org/D16528</a>)<u></u><u></u></span></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";color:black;background:white"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";color:black;background:white">Regards,<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";color:black;background:white">Igor Breger.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> Sanjay Patel [<a href="mailto:spatel@rotateright.com" target="_blank">mailto:spatel@rotateright.com</a>]
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<b>Sent:</b> Saturday, January 23, 2016 18:42<br>
<b>To:</b> Nema, Ashutosh <<a href="mailto:Ashutosh.Nema@amd.com" target="_blank">Ashutosh.Nema@amd.com</a>><br>
<b>Cc:</b> Demikhovsky, Elena <<a href="mailto:elena.demikhovsky@intel.com" target="_blank">elena.demikhovsky@intel.com</a>>; zhi chen <<a href="mailto:zchenhn@gmail.com" target="_blank">zchenhn@gmail.com</a>>; llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><br>
<b>Subject:</b> Re: [llvm-dev] how to force llvm generate gather intrinsic<u></u><u></u></span></p>
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<p class="MsoNormal">On Sat, Jan 23, 2016 at 6:45 AM, Nema, Ashutosh <<a href="mailto:Ashutosh.Nema@amd.com" target="_blank">Ashutosh.Nema@amd.com</a>> wrote:<u></u><u></u></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Thanks Sanjay for highlighting this, few days back I also faced similar problem
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">while generating masked store in avx1 mode, found its only supported under
</span><u></u><u></u></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">avx2 else we scalarize it.</span><u></u><u></u></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> </span><u></u><u></u></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">> 1) I did not switch-on masked_load/store to AVX1, I can do this.</span><u></u><u></u></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"> </span><u></u><u></u></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Yes Elena, This should be supported for FP type in avx1 mode (for INT type, I doubt X86 has masked_load/store
instruction in avx1 mode).</span><u></u><u></u></p>
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Thanks everyone for the answers. My immediate motivation is to improve the masked load/store ops for an AVX target. If we can fix scatter/gather similarly, that would be great.<br>
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Can we legalize the same set of masked load/store operations for AVX1 as AVX2? If I'm understanding them correctly, the AVX1 FP instructions (vmaskmovps/pd) can be used in place of the AVX2 int instructions (vpmaskmovd/q), just with domain crossing penalties
thrown in. I think we do this for other missing integer ops for an AVX1 target either in x86 lowering or in the tablegen patterns.<u></u><u></u></p>
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<p class="MsoNormal"> Elena - I'm not too familiar with the vectorizers or scatter/gather, but I'll certainly take a look at D15690. Thanks for pointing out the patch!<u></u><u></u></p>
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