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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Hello,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";background:white">Enabling vector masked_load/store to AVX1 using
<span class="apple-converted-space"> </span>AVX1 FP instructions (vmaskmovps/pd) in place of the AVX2 int instructions (vpmaskmovd/q)
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";background:white">committed to r258675.
<span style="color:black">(<a href="http://reviews.llvm.org/D16528">http://reviews.llvm.org/D16528</a>)<o:p></o:p></span></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";color:black;background:white"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";color:black;background:white">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Segoe UI","sans-serif";color:black;background:white">Igor Breger.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> Sanjay Patel [<a href="mailto:spatel@rotateright.com">mailto:spatel@rotateright.com</a>]
<br>
<b>Sent:</b> Saturday, January 23, 2016 18:42<br>
<b>To:</b> Nema, Ashutosh <<a href="mailto:Ashutosh.Nema@amd.com">Ashutosh.Nema@amd.com</a>><br>
<b>Cc:</b> Demikhovsky, Elena <<a href="mailto:elena.demikhovsky@intel.com">elena.demikhovsky@intel.com</a>>; zhi chen <<a href="mailto:zchenhn@gmail.com">zchenhn@gmail.com</a>>; llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>><br>
<b>Subject:</b> Re: [llvm-dev] how to force llvm generate gather intrinsic<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Sat, Jan 23, 2016 at 6:45 AM, Nema, Ashutosh <<a href="mailto:Ashutosh.Nema@amd.com" target="_blank">Ashutosh.Nema@amd.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks Sanjay for highlighting this, few days back I also faced similar problem
</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">while generating masked store in avx1 mode, found its only supported under
</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">avx2 else we scalarize it.</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">> 1) I did not switch-on masked_load/store to AVX1, I can do this.</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Yes Elena, This should be supported for FP type in avx1 mode (for INT type, I doubt X86 has masked_load/store
instruction in avx1 mode).</span><o:p></o:p></p>
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<br>
Thanks everyone for the answers. My immediate motivation is to improve the masked load/store ops for an AVX target. If we can fix scatter/gather similarly, that would be great.<br>
<br>
Can we legalize the same set of masked load/store operations for AVX1 as AVX2? If I'm understanding them correctly, the AVX1 FP instructions (vmaskmovps/pd) can be used in place of the AVX2 int instructions (vpmaskmovd/q), just with domain crossing penalties
thrown in. I think we do this for other missing integer ops for an AVX1 target either in x86 lowering or in the tablegen patterns.<o:p></o:p></p>
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<p class="MsoNormal"> Elena - I'm not too familiar with the vectorizers or scatter/gather, but I'll certainly take a look at D15690. Thanks for pointing out the patch!<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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