<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jan 15, 2016 at 1:10 PM, Krzysztof Parzyszek <span dir="ltr"><<a href="mailto:kparzysz@codeaurora.org" target="_blank">kparzysz@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><span class="">On 1/15/2016 2:57 PM, Phil Tomson wrote:<br>
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I see the following in my SelectCode (in XSTGGenDGISel.inc):<br>
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/*2235*/ OPC_SwitchOpcode /*2 cases */, 27,<br>
TARGET_VAL(XSTGISD::ADDR_NORMAL),// ->2266<br>
/*2239*/ OPC_RecordChild0, // #1 = $addr<br>
/*2240*/ OPC_MoveChild, 0,<br>
/*2242*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetGlobalAddress),<br>
/*2245*/ OPC_MoveParent,<br>
/*2246*/ OPC_MoveParent,<br>
/*2247*/ OPC_CheckPredicate, 5, // Predicate_unindexedload<br>
/*2249*/ OPC_CheckPredicate, 6, // Predicate_load<br>
/*2251*/ OPC_CheckType, MVT::i64,<br>
/*2253*/ OPC_EmitMergeInputChains1_0,<br>
/*2254*/ OPC_EmitInteger, MVT::i64, 0,<br>
/*2257*/ OPC_MorphNodeTo, TARGET_VAL(XSTG::LOADI64_RI),<br>
0|OPFL_Chain|OPFL_MemRefs,<br>
1/*#VTs*/, MVT::i64, 2/*#Ops*/, 1, 2,<br>
// Src: (ld:i64 (XSTGADDR_NORMAL:iPTR<br>
(tglobaladdr:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>><br>
- Complexity = 10<br>
// Dst: (LOADI64_RI:i64 (tglobaladdr:i64):$addr, 0:i64)<br>
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Not sure why the initial Opcode index is being set to 0 instead of 2235?<br>
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That's where matching of ADDR_NORMAL begins. Is the code matching ADDR_USE_GRP in the .inc file?</blockquote><div><br></div><div>Oh, sorry, copied the wrong section, yes it's there:<br><br>/*2266*/ /*SwitchOpcode*/ 35, TARGET_VAL(XSTGISD::ADDR_USE_GRP),// ->2304<br>/*2269*/ OPC_RecordChild0, // #1 = $addr<br>/*2270*/ OPC_MoveChild, 0,<br>/*2272*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetGlobalAddress),<br>/*2275*/ OPC_MoveParent,<br>/*2276*/ OPC_MoveParent,<br>/*2277*/ OPC_CheckPredicate, 5, // Predicate_unindexedload<br>/*2279*/ OPC_CheckPredicate, 6, // Predicate_load<br>/*2281*/ OPC_CheckType, MVT::i64,<br>/*2283*/ OPC_EmitMergeInputChains1_0,<br>/*2284*/ OPC_EmitNode, TARGET_VAL(XSTG::MOVIMMZ_I64), 0,<br> 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 1, // Results = #2<br>/*2292*/ OPC_EmitRegister, MVT::i64, XSTG::GRP,<br>/*2295*/ OPC_MorphNodeTo, TARGET_VAL(XSTG::LOADI64_RR), 0|OPFL_Chain|OPFL_MemRefs,<br> 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 2, 3, <br> // Src: (ld:i64 (XSTGADDR_USE_GRP:iPTR (tglobaladdr:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10<br> // Dst: (LOADI64_RR:i64 (MOVIMMZ_I64:i64 (tglobaladdr:i64):$addr), GRP:i64)<br>/*2304*/ 0, // EndSwitchOpcode<br><br><br><br> <br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class=""><div class="h5"><br>
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-Krzysztof<br>
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-- <br>
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<br>
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