<html><head><style type='text/css'>p { margin: 0; }</style></head><body><div style='font-family: arial,helvetica,sans-serif; font-size: 10pt; color: #000000'>[resending so the message is smaller]<br><br><hr id="zwchr"><br><br>From: "James Molloy via llvm-dev" <llvm-dev@lists.llvm.org> <br>To: "Quentin Colombet" <qcolombet@apple.com> <br>Cc: "llvm-dev" <llvm-dev@lists.llvm.org> <br>Sent: Wednesday, January 13, 2016 2:35:32 AM <br>Subject: Re: [llvm-dev] [GlobalISel] A Proposal for global instruction selection <br><br>Hi Philip, <br><br><blockquote> store <2 x i64> %1, <2 x i64>* %y <br><br>Yes. The memory pattern differs. This is the first diagram on the right at: http://llvm.org/docs/BigEndianNEON.html#bitconverts ) </blockquote><br>I think that teaching the optimizer about big-Endian lane ordering would have been better. Inserting the REV after every LDR sounds very similar to what we do for VSX on little-Endian PowerPC systems (PowerPC may have a slight advantage here in that we don't need to do insertelement / extractelement / shufflevector through memory on systems where little-Endian mode is relevant, see http://llvm.org/devmtg/2014-10/Slides/Schmidt-SupportingVectorProgramming.pdf). <br><br>Given what's been done, should we update the LangRef. It currently reads, " The ‘ bitcast ‘ instruction converts value to type ty2 . It is always a no-op cast because no bits change with this conversion. The conversion is done as if the value had been stored to memory and read back as type ty2 ." But this is now, at the least, misleading, because this process of storing the value as one type and reading it back in as another does, in fact, change the bits. We need to make clear that this might change the bits (perhaps specifically by calling out this case of vector bitcasts on big-Endian systems?). <br><br>Also, regarding this, " Most operating systems however do not run with alignment faults enabled, so this is often not an issue." Are you saying that the processor does the correct thing in this case (if alignment faults are not enabled, then it performs a proper unaligned load), or that the operating-system trap handler emulates the unaligned load should one occur? <br><br>Thanks again, <br>Hal <br>_______________________________________________ <br><blockquote>LLVM Developers mailing list <br>llvm-dev@lists.llvm.org <br>http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev <br><br></blockquote><br>-- <br>Hal Finkel<br>Assistant Computational Scientist<br>Leadership Computing Facility<br>Argonne National Laboratory<br></div></body></html>