<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jan 13, 2016 at 2:08 PM, Krzysztof Parzyszek via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><span class="">On 1/13/2016 2:26 PM, Phil Tomson via llvm-dev wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
I've got this PseudoOp defined:<br>
<br>
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>;<br>
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;<br>
<br>
<br>
let Constraints = "$dst = $addr" in { //, Uses= [GRP] in {<br>
def RelAddr : XSTGPseudo< (outs GPRC:$dst),<br>
(ins i64imm:$spoff, i64imm:$addr),<br>
"! RELADDR $spoff, $dst",<br>
[(set GPRC:$dst, (XSTGRELADDR<br>
i64:$spoff,<br>
<br>
(i64 (XSTGMVINI i64:$addr))<br>
)<br>
)]>;<br>
}<br>
</blockquote>
<br></span>
Since i64imm is an immediate, the constraint "$dst = $addr" doesn't make sense. The constraint is there to tie the input virtual register to the output virtual register, so that they will both be assigned the same physical register.<span class=""><br>
<br>
<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
GlobalAddresses get lowered to RelAddr nodes in our ISelLowering code.<br>
Now I just need to be able to expand this in our overridden<br>
expandPostRAPseudo function, however, I'm a bit worried that expansion<br>
happens too late (after things should already be MI's, it seems). So<br>
things like patterns that try to match on that XSTGMVINI would have<br>
already been matched.<br>
</blockquote>
<br></span>
The function expandPostRAPseudo is called after instruction selection, after MI-level SSA-based optimizations, after register allocation. In other words, quite late in the entire optimization sequence. Most of the actual optimization work is pretty much done at this point.<span class=""><br>
<br>
<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
[as an aside, we've got patterns like:<br>
<br>
def : Pat<(XSTGMVINI tglobaladdr:$off),<br>
(MOVIMMZ_I64 tglobaladdr:$off)>;<br>
<br>
]<br>
</blockquote>
<br></span>
I'm not sure if the input will match if you have tglobaladdr in it. The 't' means "target", and in this context it means that the argument has already been handled by the target and is in a form that does not need any further work. The lowering from globaladdr to tglobaladdr would happen after the "bigger" pattern (i.e. the one matching XSTGMVINI) has been tried, so this pattern will likely never see this combination of arguments.<span class=""><br>
<br>
<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
So, first off, if I wanted to expand that DAG for the RelAddr Node,<br>
</blockquote>
<br></span>
This is where I don't understand what you are trying to do. The machine instructions will be automatically generated and you don't have to build them yourself.<span class=""><br></span></blockquote><div><br></div><div>First off, I got this idea from the LLVM Cookbook chapter 8: Writing an LLVM Backend: Lowering to multiple instructions. (now I'm having my doubts as to whether this is the right approach)<br><br></div><div>Let me explain at the assembly level what I'm trying to accomplish.<br><br></div><div>We're trying to make position independent executables, so we intend to have a switch like -fPIE. In that case we've designated some registers to be pointers to various address spaces (and our processor is rather complicated so there are several address spaces).<br><br></div><div>Right now, given a global variable called 'answer' in C we end up with the following in the .s file:<br><br> movimm r1, %rel(answer) # r1 <- offset to 'answer' symbol<br> load r1, r1, 0 # r1<-mem[r1+0]<br><br></div><div>This isn't correct because it should be relative to the GRP register if the PIE mode is chosen, what I'd like to get is either:<br><br></div><div> movimm r1, %rel(answer)<br></div><div> addI r1, GRP # r1 <- r1 + GRP<br></div><div> load r1, r1, 0 # r1 <- mem[r1+0]<br><br></div><div>Or even better:<br><br> movimm r1, %rel(answer)<br></div><div> load r1, r1, GRP # r1 <- mem[r1+GRP]<br><br></div><div>What I'm getting at the moment is just this part:<br><br></div><div> load r1, r1, GRP<br><br></div><div>So the movimm is missing. That's because I've added the Pseudo instruction RelAddr and GlobalAddress nodes get converted to RelAddr nodes in LowerGlobalAddress.... They used to get converted to the MVINI node type there prior to adding the RelAddr pseudo inst.<br><br></div><div>It feels like more of this needs to be done in the LowerGlobalAddress function, but I have no idea how to do it there - you seem to only be able to get one instruction out of a lowering like that, not multiple instructions. It also seems like (as you point out) the expansion phase is too late to be doing it.<br></div><div> <br><br><br></div><div><br><br><br></div><div> <br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><span class="">
<br>
<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
And secondly,<br>
<br>
Would this RelAddr DAG:<br>
<br>
[(set GPRC:$dst, (XSTGRELADDR i64:$spoff,<br>
(i64<br>
(XSTGMVINI i64:$addr)<br>
)]<br>
<br>
Have been pattern matched (as per the PAT above) such that the XSTGMVINI<br>
would have been transformed into:<br>
<br>
MOVIMMZ_I64 tglobaladdr:$addr)<br>
</blockquote>
<br></span>
AFAIK, no. Global address could be matched by i64 (or an integer type that could hold it), but not the other way around.<span class=""><font color="#888888"><br>
<br>
-Krzysztof<br>
<br>
<br>
-- <br>
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<br>
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