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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Sounds like such a security-sensitive value would need to treat calls as barriers for any kind of reordering.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Also, at the end of the value's live range, it would not have to be merely dead, but dead-and-buried (i.e. overwritten) to avoid scavenging by subsequent callees.
Same goes for merely copying the value from one register to another, the source would have to be erased.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">--paulr<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> llvm-dev [mailto:llvm-dev-bounces@lists.llvm.org]
<b>On Behalf Of </b>Stephen Crane via llvm-dev<br>
<b>Sent:</b> Monday, November 02, 2015 4:08 PM<br>
<b>To:</b> Smith, Kevin B<br>
<b>Cc:</b> llvm-dev@lists.llvm.org; Per Larsen; Andrei Homescu<br>
<b>Subject:</b> Re: [llvm-dev] How to prevent registers from spilling?<o:p></o:p></span></p>
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<p class="MsoNormal">Thanks, I hadn't thought about the HPC applications. I'm not sure that the requirements for the HPC and security use-cases are compatible. Pinning for performance can tolerate spills if it is still fast, while security uses can tolerate
slow rematerialization but not spills. Maybe a shared infrastructure is possible but with variable constraints?<o:p></o:p></p>
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<p class="MsoNormal">On Mon, Nov 2, 2015 at 3:47 PM, Smith, Kevin B <<a href="mailto:kevin.b.smith@intel.com" target="_blank">kevin.b.smith@intel.com</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal">That breaks the whole IR idea of using alloca to allocate/denote space for local variables, and then optimize those<br>
into SSA values when optimization proves that is OK.<o:p></o:p></p>
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<p class="MsoNormal">Agreed, but the values I care about (which is not really the HPC use-case) would actually be values internal to the compiler, such as the location of CFI metadata, which are never exposed to the front end. Thus I would be happy with something
at the machine IR level, after that abstraction has been lost.<o:p></o:p></p>
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<p class="MsoNormal">Also, for a lot of things, that attribute is simply impossible to implement. Any value that is live across a call needs to be spilled to memory.<br>
You cannot put an unspillable value in a callee preserved register, because you cannot know whether the callee may save that or not.<br>
And if it is in a caller-save register, then the caller has to spill it if it is live across a call.<o:p></o:p></p>
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<p class="MsoNormal">Yes, but what about values that can be rematerialized? Of course values that _need_ to be live across calls are out, but I'm more concerned about values that were coalesced, hoisted, and which then get spilled. Maybe prevention of coalescing
for sensitive values and explicitly inserting materialization at each use is an option here, although that sounds like teaching a lot of passes about sensitive values, with no guarantee of finding all of them. Wouldn't the register allocator still need to
make sure that sensitive values are not present in dead callee-saved registers, so they don't get accidentally spilled by a callee?<o:p></o:p></p>
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<p class="MsoNormal">- stephen<o:p></o:p></p>
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