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</o:shapelayout></xml><![endif]--></head><body lang=EN-IE link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'>Thanks Steve, I will try this out. I hadn’t realised that TableGen was restricted to matching instructions with more than one output operand. I’m assuming that this is only a limitation for inferring an instruction from the patterns, because it does seem to manage schedules okay.<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'>Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though):<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'><span style='font-family:"Courier New";color:black'>// Memory address: 32-bit base register + 16-bit offset register<o:p></o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'><span style='font-family:"Courier New";color:black'>def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>;<o:p></o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'><span style='font-family:"Courier New";color:black'>def MEMrr : Operand<iPTR> {<o:p></o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'><span style='font-family:"Courier New";color:black'> let PrintMethod = "printMemOffsetOperand";<o:p></o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'><span style='font-family:"Courier New";color:black'> let MIOperandInfo = (ops RC32, RC16_l);<o:p></o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'><span style='font-family:"Courier New";color:black'>}<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'>but it is still happy to select for offset’s > 16-bits. There is something I am just not yet getting right, but it looks like I am on the right track.<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'>All the best,<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'> MartinO<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Steve Montgomery [mailto:stephen.montgomery3@btinternet.com] <br><b>Sent:</b> 30 October 2015 13:47<br><b>To:</b> Martin J. O'Riordan<br><b>Cc:</b> LLVM Developers<br><b>Subject:</b> Re: [llvm-dev] Questions about load/store incrementing address modes<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I’ve implemented something similar, though maybe not similar enough to be able to help you. My target supports increment and decrement, both pre and post, by an explicit constant in the range 1 to 8.<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I didn’t write any custom lowering code, just used setIndexedLoadAction() and setIndexedStoreAction() in my ISelLowering to identify the types and actions, e.g.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><span class=apple-tab-span> </span>setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I didn’t think it was possible to match an indexed load or store using a TableGen pattern because it can’t match instructions with more than one output operand, though maybe things have changed and I’ve not noticed. So, I wrote custom code in my ISelDAGToDAG to match indexed loads and store and to select these instructions. That seems to work fine for constant increments/decrements. I don’t know whether the indexed load and store actions would deal with increment or decrement by a register.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I’ve also got an addressing mode similar to yours in which an address can be formed from a 16-bit register plus a zero-extended 8-bit register. I used a ComplexPattern to match the address expression and MIOperandInfo to specify the classes of the registers, e.g.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><span class=apple-tab-span> </span>def memR16R8 : Operand<i16> {<o:p></o:p></p></div><div><p class=MsoNormal><span class=apple-tab-span> </span>let MIOperandInfo = (ops Reg16Class, Reg8Class);<o:p></o:p></p></div><div><p class=MsoNormal><span class=apple-tab-span> </span>...<o:p></o:p></p></div><div><p class=MsoNormal><span class=apple-tab-span> </span>}<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Again, this seems to work OK for me.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Steve<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal>On 30 Oct 2015, at 10:43, Martin J. O'Riordan via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'>I have a rudimentary implementation for load and store instructions, where the memory address operand is automatically post-incremented when the load or store instruction is issued. However, this is currently coded using custom lowering, and explicit pattern matching in the ‘</span><span style='font-family:"Courier New"'>ISelDAGtoDAG</span><span style='font-family:"Book Antiqua","serif"'>’ implementation. But it seems to me that I ought to be able to achieve this exclusively using TableGen with minimal custom C++ code, but I can’t quite get the patterns to work to achieve this.</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'>I have two types of post-increment:</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div style='margin-left:36.0pt'><p class=MsoNormal style='text-indent:-18.0pt'><span style='font-family:"Book Antiqua","serif"'>1.</span><span style='font-size:7.0pt'> <span class=apple-converted-space> </span></span><span style='font-family:"Book Antiqua","serif"'>increment by an implied constant which is the size of the object being loaded or stored</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div style='margin-left:36.0pt'><p class=MsoNormal style='text-indent:-18.0pt'><span style='font-family:"Book Antiqua","serif"'>2.</span><span style='font-size:7.0pt'> <span class=apple-converted-space> </span></span><span style='font-family:"Book Antiqua","serif"'>increment by the value contained in another register</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'>It should be possible to do these with the same underlying pattern, but providing a DAG fragment like ‘</span><span style='font-family:"Courier New"'>(i32 2)</span><span style='font-family:"Book Antiqua","serif"'>’ for an ‘</span><span style='font-family:"Courier New"'>i16</span><span style='font-family:"Book Antiqua","serif"'>’ load explicitly in the TableGen specialisation for the first form, and the actual register chain for the second.</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'>But I don’t seem to be quite get it to work, and in some cases the patterns I have attempted have crashed TableGen itself<span class=apple-converted-space> </span></span><span style='font-family:Wingdings'>L</span><span style='font-family:"Book Antiqua","serif"'> The incrementing store sort of works, but the incrementing load doesn’t (at least not using TableGen alone).</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'>The other form of addressing mode is where the address is a “base” plus signed “offset” register. My patterns for this work okay, but I have a limitation. The “offset” register is 16-bits, and in particular, it is the low-order 16-bits of a 32-bit actual register. But even though I have explicitly stated in TableGen that the offset register is 16-bits and stated the appropriate register class, the code-generation still uses the instructions “as if” the offset register is 32-bits.</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'>Memory addresses in this architecture are 32-bits.</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'>Has anybody solved similar problems, and have advice or examples of how to do this? Or is simply something that TableGen descriptions cannot completely describe? I have looked at the other targets for inspiration, but they don’t quite seem to do what I need.</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'>Thanks,</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> Martin O’Riordan - Movidius Ltd.</span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua","serif"'> </span><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'><o:p></o:p></span></p></div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'>_______________________________________________<br>LLVM Developers mailing list<br></span><a href="mailto:llvm-dev@lists.llvm.org"><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif";color:purple'>llvm-dev@lists.llvm.org</span></a><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif"'><br></span><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev"><span style='font-size:9.0pt;font-family:"Helvetica","sans-serif";color:purple'>http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</span></a><o:p></o:p></p></div></blockquote></div><p class=MsoNormal><o:p> </o:p></p></div></div></body></html>