<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On 2 Nov 2015, at 10:27, Martin J. O'Riordan <<a href="mailto:martin.oriordan@movidius.com" class="">martin.oriordan@movidius.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="WordSection1" style="page: WordSection1; font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Book Antiqua', serif; color: rgb(31, 73, 125);" class="">Thanks Steve, I will try this out. I hadn’t realised that TableGen was restricted to matching instructions with more than one output operand. I’m assuming that this is only a limitation for inferring an instruction from the patterns, because it does seem to manage schedules okay.</span></div></div></div></blockquote><div><br class=""></div>I’m basing my statement on the material at the end of the “Selection DAG Select Phase” in “The LLVM Target-Independent Code Generator”, <a href="http://llvm.org/docs/CodeGenerator.html#selectiondag-select-phase" class="">http://llvm.org/docs/CodeGenerator.html#selectiondag-select-phase</a>. I’ve not actually checked TableGen though so can’t be 100% sure that the documentation is still in date.</div><div><span style="color: rgb(31, 73, 125); font-family: 'Book Antiqua', serif; font-size: 12pt;" class=""> </span><br class=""><blockquote type="cite" class=""><div class="WordSection1" style="page: WordSection1; font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Book Antiqua', serif; color: rgb(31, 73, 125);" class="">Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though):<o:p class=""></o:p></span></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Book Antiqua', serif; color: rgb(31, 73, 125);" class=""><o:p class=""> </o:p></span></div><div style="margin: 0cm 0cm 0.0001pt 36pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Courier New';" class="">// Memory address: 32-bit base register + 16-bit offset register<o:p class=""></o:p></span></div><div style="margin: 0cm 0cm 0.0001pt 36pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Courier New';" class="">def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>;<o:p class=""></o:p></span></div><div style="margin: 0cm 0cm 0.0001pt 36pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Courier New';" class="">def MEMrr : Operand<iPTR> {<o:p class=""></o:p></span></div><div style="margin: 0cm 0cm 0.0001pt 36pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Courier New';" class=""> let PrintMethod = "printMemOffsetOperand";<o:p class=""></o:p></span></div><div style="margin: 0cm 0cm 0.0001pt 36pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Courier New';" class=""> let MIOperandInfo = (ops RC32, RC16_l);<o:p class=""></o:p></span></div><div style="margin: 0cm 0cm 0.0001pt 36pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Courier New';" class="">}<o:p class=""></o:p></span></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Book Antiqua', serif; color: rgb(31, 73, 125);" class=""><o:p class=""> </o:p></span></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-family: 'Book Antiqua', serif; color: rgb(31, 73, 125);" class="">but it is still happy to select for offset’s > 16-bits. There is something I am just not yet getting right, but it looks like I am on the right track.</span></div></div></blockquote><div><br class=""></div></div>I believe that the MIOperandInfo will constrain the register class for your 16-bit offset operand to RC16_1 but in itself it won’t affect the matching of the operand. Your SelectADDRrr will need to contain code to match an i32 added to a sign-extended i16. If you’ve already done that, then I’m out of ideas, sorry.<div class=""><br class=""></div><div class="">Steve</div></body></html>