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</o:shapelayout></xml><![endif]--></head><body lang=EN-IE link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>I have a rudimentary implementation for load and store instructions, where the memory address operand is automatically post-incremented when the load or store instruction is issued. However, this is currently coded using custom lowering, and explicit pattern matching in the ‘</span><span style='font-size:12.0pt;font-family:"Courier New"'>ISelDAGtoDAG</span><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>’ implementation. But it seems to me that I ought to be able to achieve this exclusively using TableGen with minimal custom C++ code, but I can’t quite get the patterns to work to achieve this.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>I have two types of post-increment:<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l1 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><span style='mso-list:Ignore'>1.<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>increment by an implied constant which is the size of the object being loaded or stored<o:p></o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l1 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><span style='mso-list:Ignore'>2.<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>increment by the value contained in another register<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>It should be possible to do these with the same underlying pattern, but providing a DAG fragment like ‘</span><span style='font-size:12.0pt;font-family:"Courier New"'>(i32 2)</span><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>’ for an ‘</span><span style='font-size:12.0pt;font-family:"Courier New"'>i16</span><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>’ load explicitly in the TableGen specialisation for the first form, and the actual register chain for the second.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>But I don’t seem to be quite get it to work, and in some cases the patterns I have attempted have crashed TableGen itself </span><span style='font-size:12.0pt;font-family:Wingdings'>L</span><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'> The incrementing store sort of works, but the incrementing load doesn’t (at least not using TableGen alone).<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>The other form of addressing mode is where the address is a “base” plus signed “offset” register. My patterns for this work okay, but I have a limitation. The “offset” register is 16-bits, and in particular, it is the low-order 16-bits of a 32-bit actual register. But even though I have explicitly stated in TableGen that the offset register is 16-bits and stated the appropriate register class, the code-generation still uses the instructions “as if” the offset register is 32-bits.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>Memory addresses in this architecture are 32-bits.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>Has anybody solved similar problems, and have advice or examples of how to do this? Or is simply something that TableGen descriptions cannot completely describe? I have looked at the other targets for inspiration, but they don’t quite seem to do what I need.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'> Martin O’Riordan - Movidius Ltd.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua","serif"'><o:p> </o:p></span></p></div></body></html>