<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Sep 22, 2015, at 1:12 AM, Sky Flyer via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div class=""><div class=""><div class=""><div class=""><div class="">Hi all,<br class=""><br class=""></div>what is exactly "zero_reg"?<br class=""><br class="">from ARMInstFromats.td:<br class=""><br class=""><b class="">def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> {...}</b><br class=""><br class=""></div>I thought zero_reg can be replace by a random name like (alu_stat_reg for alu state register) but when I compiled it, I figure out that zero_reg is a predefined variable.<br class=""><br class=""></div>Can someone please give me more information about zero_reg and if possible more about PredicateOperand operands.<br class=""><br class=""></div>Cheers,<br class=""></div>ES<br class=""></div>
_______________________________________________<br class="">LLVM Developers mailing list<br class=""><a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a><br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev<br class=""></div></blockquote></div><br class=""><div class=""><br class=""></div><div class="">This corresponds to NoRegister (this could use a rename). It allows you to emit an operand an an instruction pattern with an invalid register value which presumably something else expects to fill in later.</div><div class=""><br class=""></div><div class=""><br class=""></div></body></html>