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<p class="MsoNormal"><span style="color:#1F497D">The initial thought I had was that I could ignore the ASR18 and Y registers, but the SMAC instruction is designed to be used in a loop and ASR18 (and Y) feed back into the inputs each time too.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Does this imply that a hand-coded ISelDAGToDAG.cpp implementation is going to be virtually required?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Any chance of some Pseudo-code? I haven’t had to write any ISelDAGToDAG code up to now and any starter would be appreciated.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="mso-fareast-language:EN-IE">From:</span></b><span lang="EN-US" style="mso-fareast-language:EN-IE"> Hal Finkel [mailto:hfinkel@anl.gov]
<br>
<b>Sent:</b> 18 September 2015 15:46<br>
<b>To:</b> Chris.Dewhurst<br>
<b>Cc:</b> llvm-dev@lists.llvm.org<br>
<b>Subject:</b> Re: [llvm-dev] multiply-accumulate instruction<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:black;mso-fareast-language:EN-IE"><o:p> </o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><b><span style="font-family:"Helvetica","sans-serif";color:black">From:
</span></b><span style="font-family:"Helvetica","sans-serif";color:black">"Chris.Dewhurst via llvm-dev" <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>><br>
<b>To: </b><a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a><br>
<b>Sent: </b>Friday, September 18, 2015 9:19:48 AM<br>
<b>Subject: </b>[llvm-dev] multiply-accumulate instruction</span><span style="font-size:12.0pt;font-family:"Helvetica","sans-serif";color:black;mso-fareast-language:EN-IE"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black">I’m trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black">The documentation for the processor is as follows:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black">===<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black">To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator
made up by the 8 lsb bits from the %y register and the %asr18 register. The least significant 32 bits are also written to the destination register. SMAC works similarly but performs signed multiply and accumulate. The MAC instructions execute in one clock
but have two clocks latency, meaning that one pipeline stall cycle will be inserted if the following instruction uses the destination register of the MAC as a source operand.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black">Assembler syntax:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> smac rs1, reg_imm, rd<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black">Operation:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> prod[31:0] = rs1[15:0] * reg_imm[15:0]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> result[39:0] = (Y[7:0] & %asr18[31:0]) + prod[31:0]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> (Y[7:0] & %asr18[31:0]) = result[39:0]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> rd = result[31:0]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black">%asr18 can be read and written using the rdasr and wrasr instructions.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black">===<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black">I have the following in SparcInstrInfo to define the lowering rules for this instruction, but I feel that this isn’t likely to work as I need to somehow tie together the fact that %Y, %ASR18 and %rd are all related
to each other in the output.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black">let Predicates = [HasLeon3, HasLeon4], Defs = [Y, ASR18], Uses = [Y, ASR18] in</span><span style="color:black"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black">def SMACrr : F3_1<3, 0b111110,</span><span style="color:black"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black"> (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),</span><span style="color:black"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black"> "smac $rs1, $rs2, $rd",</span><span style="color:black"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black"> [(set i32:$rd,</span><span style="color:black"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black"> (add i32:$asr18, (mul i32:$rs1, i32:$rs2)))] >;</span><span style="color:black"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black"> </span><span style="color:black"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black">Perhaps a well-chosen “let Constraints=” might be used here? If so, I’m not sure I know what to put in there. If not, can anyone help me how I might define the lowering
rules for this instruction please?</span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:black;mso-fareast-language:EN-IE">You don't need to encode that relationship if the values placed in Y and ASR18 will be ignored. If you want to use those results, I suspect
that you'll need to manually select the instruction in *ISelDAGToDAG.cpp, grabbing the result from the fixed registers by generating a glued CopyFromReg node.<br>
<br>
-Hal<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black"> </span><span style="color:black"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Courier New";color:black">Chris Dewhurst, University of Limerick.</span><span style="color:black"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Helvetica","sans-serif";color:black;mso-fareast-language:EN-IE"><br>
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<br>
<br>
-- <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:black;mso-fareast-language:EN-IE">Hal Finkel<br>
Assistant Computational Scientist<br>
Leadership Computing Facility<br>
Argonne National Laboratory<o:p></o:p></span></p>
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