<html><head><style type='text/css'>p { margin: 0; }</style></head><body><div style='font-family: arial,helvetica,sans-serif; font-size: 10pt; color: #000000'><br><hr id="zwchr"><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><b>From: </b>"Chris.Dewhurst via llvm-dev" <llvm-dev@lists.llvm.org><br><b>To: </b>llvm-dev@lists.llvm.org<br><b>Sent: </b>Friday, September 18, 2015 9:19:48 AM<br><b>Subject: </b>[llvm-dev] multiply-accumulate instruction<br><br>
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<p class="MsoNormal">I’m trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">The documentation for the processor is as follows:</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">===</p>
<p class="MsoNormal">To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made up by the 8 lsb
bits from the %y register and the %asr18 register. The least significant 32 bits are also written to the destination register. SMAC works similarly but performs signed multiply and accumulate. The MAC instructions execute in one clock but have two clocks latency,
meaning that one pipeline stall cycle will be inserted if the following instruction uses the destination register of the MAC as a source operand.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">Assembler syntax:</p>
<p class="MsoNormal"> smac rs1, reg_imm, rd</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">Operation:</p>
<p class="MsoNormal"> prod[31:0] = rs1[15:0] * reg_imm[15:0]</p>
<p class="MsoNormal"> result[39:0] = (Y[7:0] & %asr18[31:0]) + prod[31:0]</p>
<p class="MsoNormal"> (Y[7:0] & %asr18[31:0]) = result[39:0]</p>
<p class="MsoNormal"> rd = result[31:0]</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">%asr18 can be read and written using the rdasr and wrasr instructions.</p>
<p class="MsoNormal">===</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">I have the following in SparcInstrInfo to define the lowering rules for this instruction, but I feel that this isn’t likely to work as I need to somehow tie together the fact that %Y, %ASR18 and %rd are all related to each other in the
output.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Monospace;">let Predicates = [HasLeon3, HasLeon4], Defs = [Y, ASR18], Uses = [Y, ASR18] in</span></p>
<p class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Monospace;">def SMACrr : F3_1<3, 0b111110,</span></p>
<p class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Monospace;"> (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),</span></p>
<p class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Monospace;"> "smac $rs1, $rs2, $rd",</span></p>
<p class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Monospace;"> [(set i32:$rd,</span></p>
<p class="MsoNormal"><span style="font-size: 10pt; font-family: Monospace;"> (add i32:$asr18, (mul i32:$rs1, i32:$rs2)))] >;</span></p>
<p class="MsoNormal"><span style="font-size: 10pt; font-family: Monospace;"> </span></p>
<p class="MsoNormal"><span id="DWT10677" style="font-size: 10pt; font-family: Monospace;">Perhaps a well-chosen “let Constraints=” might be used here? If so, I’m not sure I know what to put in there. If not, can anyone help me how I might define the lowering rules for this
instruction please?</span></p></div></blockquote>You don't need to encode that relationship if the values placed in Y and ASR18 will be ignored. If you want to use those results, I suspect that you'll need to manually select the instruction in *ISelDAGToDAG.cpp, grabbing the result from the fixed registers by generating a glued CopyFromReg node.<br><br> -Hal<br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><div class="WordSection1"><p class="MsoNormal"><span style="font-size: 10pt; font-family: Monospace;"></span></p>
<p class="MsoNormal"><span style="font-size: 10pt; font-family: Monospace;"> </span></p>
<p class="MsoNormal"><span style="font-size: 10pt; font-family: Monospace;">Chris Dewhurst, University of Limerick.</span></p>
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<br>_______________________________________________<br>LLVM Developers mailing list<br>llvm-dev@lists.llvm.org<br>http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev<br></blockquote><br><br><br>-- <br><div><span name="x"></span>Hal Finkel<br>Assistant Computational Scientist<br>Leadership Computing Facility<br>Argonne National Laboratory<span name="x"></span><br></div></div></body></html>