<div dir="ltr"><div><div><div>Hi Benoit -<br><br></div>I've been looking at memcpy/memset lowering and alignment issues recently. See:<br><a href="https://llvm.org/bugs/show_bug.cgi?id=24678">https://llvm.org/bugs/show_bug.cgi?id=24678</a><br></div>and the links from there. <br><br>If you can file a bug report with your test case and any perf data that you've collected, that would be very helpful.<br><br></div>Thanks!<br><div><div><br><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Sep 8, 2015 at 12:11 PM, Benoit Belley via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
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<div>Hi Philip,</div>
<div><br>
</div>
<div>Attached you will find the LLVM IR that causes LLVM 3.7.0 to emit assembly generating a whole bunch of blocked store-forwarding pipeline stalls. </div>
<div><br>
</div>
<div>Compile using:</div>
<div><br>
</div>
<div><span style="white-space:pre-wrap"></span><span style="font-family:Consolas;font-size:14px">$ llvm/3.7.0/Release/bin/opt -S -O3 store-forward-failure.ll -o - | llvm/3.7.0/Release/bin/llc -filetype=asm -O3 -o -</span></div>
<div><span style="font-family:Consolas;font-size:14px"><br>
</span></div>
<div><span style="font-family:Consolas;font-size:14px"><br>
</span></div>
<div>You will find assembly sequences such as:</div>
<div>
<div><br>
</div>
<div> movss dword ptr [rcx - 12], xmm4 # 32-bit store</div>
<div> movss dword ptr [rcx - 16], xmm3 # 32-bit store</div>
<div> <span style="white-space:pre-wrap"></span>mov<span style="white-space:pre-wrap">
</span>rdx, qword ptr [rcx - 16] # 64-bit load</div>
<div><br>
</div>
<div>Notice how the stores and loads are back-to-back and of different bit-width. On my processor (Intel Sandy Bridge), this sequence seems to fail store-forwarding and to cause a huge CPU pipeline stall. Or at least, this is what the following CPU performance
counter leads me to believe:</div>
<div><br>
</div>
<div><span style="white-space:pre-wrap"></span>LD_BLOCKS.STORE_FORWARD: Loads blocked by overlapping with store buffer that cannot be forwarded.</div>
<div><br>
</div>
<div>My test case is generating 1,500,000,000 of these "blocked store-forwarding » when using LLVM 3.7 versus 74,000 for LLVM 3.6! The number of instructions executed per CPU cycles goes down to 0.7 IPC instead of 2.2 IPC.</div>
</div>
<div><br>
</div>
<div>Further analysis suggests that it might be due to the GVN pass (which runs just before the MemCpy pass) which actually combines 2 32-bit loads into a single 64-bit load. See the attached files.</div>
<div><br>
</div>
<div>I have also noted that the alloca are actually getting properly annotated with an alignment of 8 bytes by the « Combine redundant instructions » pass. So, I guess that annotating alloca when emitting LLVM IR within our JIT compiler is unnecessary. Is that
a fair assessment ?</div>
<div><br>
</div>
<div>Is store-forwarding always blocking on these kind of memory accesses even if they are properly aligned ?</div>
<div><br>
</div>
<div>(Side note: Moving the alloca into the entry BB, causes all of these redundant alloca, store and load instructions to be optimized out and the entire store-forwarding issue goes away for this particular test case. But, isn’t this an issue that could be
triggered in other valid cases ?) </div><span class="">
<div><br>
</div>
<div>Cheers, </div>
<div>Benoit</div>
<div><br>
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<span style="font-weight:bold">From: </span>llvm-dev <<a href="mailto:llvm-dev-bounces@lists.llvm.org" target="_blank">llvm-dev-bounces@lists.llvm.org</a>> on behalf of Benoit Belley via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><br>
<span style="font-weight:bold">Reply-To: </span>Benoit Belley <<a href="mailto:benoit.belley@autodesk.com" target="_blank">benoit.belley@autodesk.com</a>><br>
<span style="font-weight:bold">Date: </span>mardi 8 septembre 2015 13:11<br>
<span style="font-weight:bold">To: </span>Philip Reames <<a href="mailto:listmail@philipreames.com" target="_blank">listmail@philipreames.com</a>>, "<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>" <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><div><div class="h5"><br>
<span style="font-weight:bold">Subject: </span>Re: [llvm-dev] LLVM struct, alloca, SROA and the entry basic block<br>
</div></div></div><div><div class="h5">
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<blockquote style="BORDER-LEFT:#b5c4df 5 solid;PADDING:0 0 0 5;MARGIN:0 0 0 5">
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<div><span style="font-family:Calibri;font-size:11pt;font-weight:bold">From:
</span><span style="font-family:Calibri;font-size:11pt">Philip Reames <</span><a href="mailto:listmail@philipreames.com" style="font-family:Calibri;font-size:11pt" target="_blank">listmail@philipreames.com</a><span style="font-family:Calibri;font-size:11pt">></span></div>
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<span style="font-weight:bold">Date: </span>mardi 8 septembre 2015 12:50<br>
<span style="font-weight:bold">To: </span>Benoit Belley <<a href="mailto:benoit.belley@autodesk.com" target="_blank">benoit.belley@autodesk.com</a>>, "<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>" <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><br>
<span style="font-weight:bold">Subject: </span>Re: [llvm-dev] LLVM struct, alloca, SROA and the entry basic block<br>
</div>
<div><br>
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<blockquote style="BORDER-LEFT:#b5c4df 5 solid;PADDING:0 0 0 5;MARGIN:0 0 0 5">
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<div>On 09/08/2015 07:21 AM, Benoit Belley via llvm-dev wrote:<br>
</div>
<blockquote type="cite">
<div style="color:rgb(0,0,0);font-family:Calibri,sans-serif;font-size:16px">
Hi everyone,</div>
<div style="color:rgb(0,0,0);font-family:Calibri,sans-serif;font-size:16px">
<br>
</div>
<div style="color:rgb(0,0,0);font-family:Calibri,sans-serif;font-size:16px">
We have noticed that the SROA pass will only eliminate ‘alloca’ instructions if those are located in the entry basic block of a function.</div>
<div style="color:rgb(0,0,0);font-family:Calibri,sans-serif;font-size:16px">
<br>
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<div><i><font face="Calibri,sans-serif"><b>As a general recommendation, should the LLVM IR emitted by our compiler always place ‘alloca’ instructions in the entry basic block ? (I couldn’t find any recommendations concerning this matter.)</b></font></i></div>
</blockquote>
<font face="Calibri,sans-serif">Yes. </font><br>
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<div>Thanks Phil. Should this be mentioned somewhere in the documentation ? As a footnote in the LLVM Language Reference manual maybe ?</div>
<div><br>
</div>
<div>As a note, I have also find out that alloca instructions should be placed before any call instructions as these can get inlined and then, the original alloca can no longer by placed in the entry basic block!</div>
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<div><font face="Calibri,sans-serif">In addition, we have noticed that the MemCpy pass will attempt to copy LLVM struct using moves that are as large as possible. </font>For example, a struct of 3 floats is copied using a 64-bit and a 32-bit move. It is therefore
important that such a struct be aligned on 8-byte boundary, not just 4 bytes! Else, one runs the risk of triggering store-forwarding failure pipelining stalls (which we did encountered really badly with one of our internal performance benchmark).</div>
</blockquote>
This sounds like a bug to me. We shouldn't be using the large load/stores without knowing they're aligned or that unaligned access is fast on a particular target. Where this is best fixed (memcpy, store lowering?) I don't know.
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<div>I’ll send out a test case. Maybe, that will help.</div>
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<div><b><i>Is there any guidelines for specifying the alignment of LLVM structs allocated by alloca instructions ? Is rounding down to the structure size to the next power of 2 a good strategy ? Will the MemCpy pass issue moves of up to 64-bytes on AVX-512
capable processors ?</i></b></div>
<div><b><i><br>
</i></b></div>
<div>Cheers,</div>
<div>Benoit<i style="font-weight:bold"> </i></div>
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