<div dir="ltr"><div>Quentin,</div><div><br></div><div> I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls:</div><div><br></div><div>const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType());</div><div>VReg = MRI->createVirtualRegister(RC);</div><div><br></div><div>My question is why is it using the SimpleValueType to define the register class instead of the actual register class defined in the td? What am I missing here?</div><div><br></div><div>Thanks!</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 24, 2015 at 8:58 PM, Ryan Taylor <span dir="ltr"><<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div>Quentin,</div><div><br></div><div> This is the issue. Somewhere prior to the constrainRegClass, it's assigning the GPRBase sub class of GPR to the MOV instruction, so it can't constrain it to Base and hence has to add the COPY. Now I just need to find out why it is ignoring the TableGen defined GPRBase for the MOV MI in favor of it's sub class GPR.</div><div><br></div><div>Thanks.</div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 24, 2015 at 8:34 PM, Ryan Taylor <span dir="ltr"><<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div>Quentin,</div><div><br></div><div> It looks like firstCommonClass is returning a nullptr, which is odd since the MOV should be using GPRBase (GPR and Base) and the NewVReg class is Base. Maybe the ISel has decided to select the sub class GPR from GPRBase and hence GPR != Base and so the constrainRegClass is failing. </div><div><br></div><div> Using the MI Op's reg class and comparing it directly to the NewVReg class would eliminate this possible issue and should produce more accurate results?</div><div><br></div><div>Thanks.</div></div><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 24, 2015 at 8:08 PM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word"><br><div><div><div><blockquote type="cite"><div>On Aug 24, 2015, at 4:46 PM, Ryan Taylor <<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>> wrote:</div><br><div><div dir="ltr"><div>Here is the snippet that matters:</div><div><br></div><div>void<br>InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,<br> SDValue Op,<br> unsigned IIOpNum,<br> const MCInstrDesc *II,<br> DenseMap<SDValue, unsigned> &VRBaseMap,<br> bool IsDebug, bool IsClone, bool IsCloned) {<br> //llvm::errs() << "Op = ";<br> //Op.dump();<br> assert(Op.getValueType() != MVT::Other &&<br> Op.getValueType() != MVT::Glue &&<br> "Chain and glue operands should occur at end of operand list!");<br> // Get/emit the operand.<br> unsigned VReg = getVR(Op, VRBaseMap);<br> assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");</div><div> const MCInstrDesc &MCID = MIB->getDesc();<br> bool isOptDef = IIOpNum < MCID.getNumOperands() &&<br> MCID.OpInfo[IIOpNum].isOptionalDef();</div><div> // If the instruction requires a register in a different class, create<br> // a new virtual register and copy the value into it, but first attempt to<br> // shrink VReg's register class within reason. For example, if VReg == GR32<br> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.<br> if (II) {<br> const TargetRegisterClass *DstRC = nullptr;<br> if (IIOpNum < II->getNumOperands())<br> DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));<br> if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {<br> unsigned NewVReg = MRI->createVirtualRegister(DstRC);<br> if (TRI->getCommonSubClass(DstRC,<br> TRI->getRegClass(II->OpInfo[IIOpNum].RegClass))<br></div></div></div></blockquote><div><br></div></div></div><div>What I was saying was this II->OpInfo[IIOpNum].RegClass looks to return DstRC at first glance.</div><div>What you want is TRI->getRegClass(VReg).</div><div><br></div><div>BTW, now with the full snippet, I see your mistake. You are passing a RegClass to a method that expect a virtual register (your call is to TargetRegisterInfo::getRegClass I believe, not MCRegisterInfo::getRegClass). So you end up with the regclass of a virtual register numbered RegClass.</div><div><br></div><div>Anyway, if we cannot constrain VReg on DstRC (i.e., what we try in the previous if), this means that getCommonSubClass will fail or will return a class that is likely too small to be reasonable (i.e., below MinRCSize).</div><div><br></div><div>Cheers,</div><div>-Quentin</div><div><div><div><br></div><br><blockquote type="cite"><div><div dir="ltr"><div> == DstRC) {<br> MRI->setRegClass(VReg, DstRC);<br> }<br> else {<br> BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),<br> TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);<br> VReg = NewVReg;<br> }<br> }</div><div> }</div><div><br></div><div>This does not work. The logic seems sound though, you are checking an RC (DstRC) and the MI's operand's RegClass, get the common sub, which should either be or not be DstRC, right?</div><div><br></div><div>Thanks.<br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 24, 2015 at 4:44 PM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><br><div><span><blockquote type="cite"><div>On Aug 24, 2015, at 1:30 PM, Ryan Taylor <<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>> wrote:</div><br><div><div dir="ltr"><div>I'm trying to do something like this:</div><div><br></div><div>// Dst = NewVReg's reg class</div><div>// *II = MCInstrDesc</div><div>// IIOpNum = II Operand Num</div><div><br></div><div>if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC)</div><div> MRI->setRegClass(VReg, DstRC);</div><div>else</div><div> BuildMI(... TargetOpcode::COPY...)</div><div><br></div><div>The condition is trying to reset the reg class if the DstRC reg class is valid for the operand num of the machine instruction. If the NewVReg register class is not valid for that operand of the machine instruction I want to generate a COPY instruction (as it does now all the time). This condition should check for intersection, right?</div></div></div></blockquote><div><br></div></span><div>Yes, that’s right.</div><span><br><blockquote type="cite"><div><div dir="ltr"><div> It should find the common subclass of the new register class and the valid reg class of the operand for that machine instruction.</div><div><br></div><div>Unfortunately it looks like that condition is always being set to true (or I'm getting a TON of false positives).</div></div></div></blockquote><div><br></div></span><div>Where does II come from?</div><div>From the snippet, I am guessing it is the instruction that uses NewVReg, i.e., you are checking that the class for NewVReg matches the class for NewVReg… which by construction is always true!</div><div><br></div><div>You want to check "common subclass” of DstRC and SrcRC.</div><div><br></div><div>Cheers,</div><div>Q.</div><div><div><br><blockquote type="cite"><div><div dir="ltr"><div><br></div><div>Thanks.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 24, 2015 at 2:09 PM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid"><div><br><div><span><blockquote type="cite"><div>On Aug 22, 2015, at 9:10 AM, Ryan Taylor <<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>> wrote:</div><br><div><div dir="ltr"><div>One last question regarding this please.</div><div><br></div><div>Why aren't we simply changing the register class in AddRegisterOperand instead of building a new COPY? I admit I haven't thought this out but for my test cases so far this works just fine and reduces the number of ASM mov instructions that are being produced.</div><div><br></div><div>For example, instead of BuildMI(..., TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg), use something like MRI->setRegClass(VReg, MRI->getRegClass(NewVReg)) ?</div></div></div></blockquote><div><br></div></span><div>The problem is that the old register class and the new one may not intersect. I do not know exactly what makes us create a new vreg w.r.t., but probably if the class is not identical we create one. You can try to use contraintsRegClass to get the intersection.</div><span><font color="#888888"><div><br></div><div>Q.</div></font></span><div><div><br><blockquote type="cite"><div><div dir="ltr"><div><br></div><div>What is the reasoning behind adding the extra instruction instead of changing the reg class? </div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Aug 19, 2015 at 2:04 PM, Ryan Taylor <span dir="ltr"><<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid"><div dir="ltr"><div>Yes, you're probably right about the ID. The odd part is that I have other simpler instructions that use the same type of superset and it always, so far, matches correctly (it doesn't just pick GPRRegs all the time).</div><div><br></div><div>Like I said, we can just 'fill in the gaps' with new MIs but that sure seems like a brush off solution. The td files would be so much cleaner if you could have a superset reg class that actually matched the correct reg usage (which it sort of does in AddRegisterOperand when it adds the extra COPY.... not sure why it does this instead of just checking the original MI and seeing if the reg class needed is in the list and then just changing the vreg reg class for the original MI, that seems like a better solution?) It's like it's actually picking some reg class first and then trying to fix it's error by adding MORE instructions instead of finding the right reg class the first time.</div><div><br></div><div>Thanks.</div></div><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Aug 19, 2015 at 1:32 PM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid"><div><br><div><span><blockquote type="cite"><div>On Aug 19, 2015, at 9:42 AM, Ryan Taylor <<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>> wrote:</div><br><div><div dir="ltr"><div>It seems the problem arises from using multiple reg classes for one MI in the td file, I guess.</div></div></div></blockquote><div><br></div></span><div>Probably, that does not sound something used widely :).</div><span><div><br></div><br><blockquote type="cite"><div><div dir="ltr"><div> I'm not sure it takes first available, if I swap the reg classes in the list it does not change and if I replace the GPR reg class with something different than it picks the base reg class fine, potentially it is using the reg class with most available? idk.</div></div></div></blockquote><div><br></div></span><div>My guess is it would take the register class that come first in the register class IDs (not the list on the instruction itself), but I am just guessing.</div><div><div><br><blockquote type="cite"><div><div dir="ltr"><div><br></div><div>I just need to create MIs for every possible case I guess. </div><div>Thanks for the help! :)</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Aug 19, 2015 at 12:04 PM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid"><div><div>Hi Ryan,</div><br><div><span><blockquote type="cite"><div>On Aug 19, 2015, at 6:35 AM, Ryan Taylor via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:</div><br><div><div dir="ltr"><div>Essentially it doesn't appear that the reg class assignment is based on uses and is instead inserting an extra COPY for this. Is this accurate? If so, why?</div></div></div></blockquote><div><br></div></span><div>We match the instructions bottom-up and I believe that copy are automatically inserted when the register classes do not match.</div><div>That seems strange to me that the isel logs are exactly the same but still you are seeing a different result of instruction selection.</div><span><br><blockquote type="cite"><div><div dir="ltr"><div><br></div><div>In this above example, I'm getting an extra "mov %r0, $b1" (this is an MI::COPY) even though "mov @a, %b1" (this is an MI::MOV) is entirely acceptable since both GPRRegs and BaseRegs are in the reg class list..</div><div><br></div><div>If the heuristic is simply picking the first available reg class or the reg class with the most available, for example, instead of picking the reg class based on uses, I will have to change this heuristic to reduce code bloat, or we'll have to add backend passes to reduce the code bloat.</div></div></div></blockquote><div><br></div></span><div>I think the current approach is rather simple and we just match the type for the first available reg class (assuming your selection dag patterns are not choosing something different). There are not per say passes to reduce this "code bloat” since we never encounter this problem in practice. The peephole optimizer has some logic to avoid this move and CodeGenPrepare also does a few transformation to avoid some of that.</div><div><br></div><div>Anyhow, I’d say debug the isel process (probably the InstrEmitter part) to see where the problem arise.</div><div><br></div><div>Cheers,</div><div>-Quentin</div><br><blockquote type="cite"><div><div><div><div dir="ltr"><div><br></div><div>Thanks.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 17, 2015 at 7:00 PM, Ryan Taylor <span dir="ltr"><<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid"><div dir="ltr"><br><div class="gmail_quote">---------- Forwarded message ----------<br>From: <b class="gmail_sendername">Ryan Taylor</b> <span dir="ltr"><<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>></span><br>Date: Mon, Aug 17, 2015 at 6:59 PM<br>Subject: Re: [LLVMdev] TableGen Register Class not matching for MI in 3.6<br>To: Quentin Colombet <<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>><br>Cc: "<a href="mailto:llvmdev@cs.uiuc.edu" target="_blank">llvmdev@cs.uiuc.edu</a>" <<a href="mailto:llvmdev@cs.uiuc.edu" target="_blank">llvmdev@cs.uiuc.edu</a>><br><br><br><div dir="ltr"><div>The isel logs are exactly the same, nothing changed, it's matching the same instructions just the reg classes are different.</div><div><br></div><div>Where in the SelectionDAG is the code that adds an extra MI COPY? I'll have to set a breakpoint and debug backwards from there to see what's going on. It's only happening with the GPRRegs class, for example if I use another reg class instead along with the base regs than it matches the base reg just fine, it's like GPR is overriding any other reg class matching.</div><div><br></div><div>Thanks.</div></div><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jul 31, 2015 at 1:21 PM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid"><div><br><div><span><blockquote type="cite"><div>On Jul 31, 2015, at 10:14 AM, Ryan Taylor <<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>> wrote:</div><br><div><div dir="ltr"><div>Quentin,</div><div><br></div><div> It's in the instruction selection, sorry I forgot to mention that. The Vreg class is GPR and an extra COPY is generated to copy from the GPR to the Base Reg, even though my 'mov' instruction has Base in the Register class list.</div></div></div></blockquote><div><br></div></span><div>Then, I suggest you use -debug-only=isel to check what changed in your selection instruction process. I do not see off-hand what could have caused.</div><div><br></div><div>Sorry for not being more helpful here.</div><span><font color="#888888"><div><br></div><div>Q.</div></font></span><div><div><br><blockquote type="cite"><div><div dir="ltr"><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jul 31, 2015 at 12:50 PM, Quentin Colombet <span dir="ltr"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid">Hi Ryan,<br>
<br>
Could you check where those moves come from?<br>
<br>
In particular, is this the product of the instruction selection process?<br>
<br>
You use -print-machineinstrs to see when it is inserted.<br>
<br>
Thanks,<br>
-Quentin<br>
<div><div><br>
> On Jul 30, 2015, at 2:02 PM, Ryan Taylor <<a href="mailto:ryta1203@gmail.com" target="_blank">ryta1203@gmail.com</a>> wrote:<br>
><br>
> In LLVM 3.6,<br>
><br>
> We have an instruction that uses a register class that is defined of several different reg classes. In 3.4 this works fine but in 3.6 this is broken.<br>
><br>
> For example, I have a mov instruction. mov can be executed between different register types (ie gpr, index, base, etc..)<br>
><br>
> In 3.4, we would get something like this:<br>
><br>
> mov @a, %b1 // moving this immediate to a base register, which is what we want<br>
><br>
> In 3.6, we now get this:<br>
><br>
> mov @a, %r0 // r0 = gpr<br>
> mov %r0, %b1 // b1 = base reg<br>
><br>
> The register class looks like this:<br>
><br>
> def ARegs : RegisterClass<"us", [i16], i16, (add GPRRegs, IndexRegs, BaseRegs)>;<br>
><br>
> I have absolutely no idea why this is not matching any longer?<br>
><br>
> The fix here is to define an MI with explicit single register class (ie it only allows PTRRegs as the destination).<br>
><br>
> This must be an issue with something else and not the tablegen but if that was the case I'm not sure. Anyway help would be great, what should I be looking at here?<br>
><br>
> Thanks.<br>
</div></div>> _______________________________________________<br>
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