<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><div class="">What are the predecessors and successors of your new basic block C? Depending on how you change the control flow it may be necessary to create new SSA value numbers in the live intervals.</div><div class=""><br class=""></div><div class="">- Matthias</div><br class=""><div><blockquote type="cite" class=""><div class="">On Aug 18, 2015, at 11:08 AM, Ziqiang Patrick Huang via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Hi all, <div class=""><br class=""></div><div class="">Suppose I have two basic blocks A->B and I want to insert a new basic block C between A and B, so that A->C->B. Right now I'm able to insert the block and correctly update the SlotIndexes. But I'm having trouble updating the LiveIntervals, so at very least I have to make sure all registers that are live in into B are live through C.</div><div class=""><br class=""></div><div class="">Suppose after inserting C the Slot Index range for the 3 blocks are </div><div class=""><br class=""></div><div class="">A [0, 20]</div><div class="">C [28, 40]</div><div class="">B [44, 60]</div><div class=""><br class=""></div><div class="">and the liveInterval of %verg 1 is (4r, 52r). So right now the liveInterval already covers C, but later I'm failing an assertion in LiveIntervals::shrinkToUses() function.</div><div class=""><br class=""></div><div class="">// Make sure VNI is live-out from the predecessors. <br class=""></div><div class=""> for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),</div><div class=""> PE = MBB->pred_end(); PI != PE; ++PI) {</div><div class=""> if (!LiveOut.insert(*PI))</div><div class=""> continue;</div><div class=""> SlotIndex Stop = getMBBEndIdx(*PI);</div><div class=""> <font color="#ff0000" class=""> assert(li->getVNInfoBefore(Stop) == VNI &&</font></div><div class=""><font color="#ff0000" class=""> "Wrong value out of predecessor");</font></div><div class=""> WorkList.push_back(std::make_pair(Stop, VNI));</div><div class=""> }</div><div class=""><br class=""></div><div class="">so I print out li here and it's (4r, 28B) [44B, 52r), so at some point the live interval of %vreg 1 is split and LLVM has no idea that register live through C, which means I must have missed updating something when I create C. </div><div class=""><br class=""></div><div class="">I'm doing this in MachineScheduler Pass,</div><div class=""><br class=""></div><div class="">Dear Cameron, I CC you because when I google to find some clue, I noticed you submit a patch for MachineBasicBlock::SplitCriticalEdge() on updating liveIntervals, so I thought maybe you might be able to help me. I tried the same method you did but still did not pass that assertion.</div><div class=""><br class=""></div><div class="">Thanks in advance,</div><div class="">Patrick </div><div class=""><br class=""></div></div>
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