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I'm not sure what the OP requirements are. That's what I was trying
to clarify/understand. I certainly don't have that requirement for
my VM, but I can't speak for the OP. <br>
<br>
Philip<br>
<br>
<div class="moz-cite-prefix">On 08/07/2015 04:47 PM, Jonathan S.
Shapiro via llvm-dev wrote:<br>
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cite="mid:CAAP=3QNskXENKngarU0zJOOFSC8_44EiDx2Zw1_cbvz_QX=vtg@mail.gmail.com"
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<div class="gmail_extra">Philip:</div>
<div class="gmail_extra"><br>
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<div class="gmail_extra">And just as an aside, I suspect I
understand why the register spill issue is important. My guess
would be that you have a need to keep your VM stack in a state
that is bitwise compliant with some external specification at
every point where a sequence point potentially exists?</div>
<div class="gmail_extra"><br>
</div>
<div class="gmail_extra">shap</div>
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