<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Jun 29, 2015, at 8:57 PM, Jingyue Wu <<a href="mailto:jingyue@google.com" class="">jingyue@google.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Hi Adam, <div class=""><br class=""></div><div class="">Indvar widening can sometimes be harmful for architectures (e.g. NVPTX and AMDGPU) where wider integer operations are more expensive (<a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__llvm.org_bugs_show-5Fbug.cgi-3Fid-3D21148&d=AwMFAg&c=8hUWFZcy2Z-Za5rBPlktOQ&r=Mfk2qtn1LTDThVkh6-oGglNfMADXfJdty4_bhmuhMHA&m=zeV6KKo_4QmNrl7a8HKbs0ceMMnzmsjyYtXh-iIkOjs&s=NsEjJmh2mla628-d4vg7gUhJvC6SjjNVxi6LB_E7gNk&e=" class="">https://llvm.org/bugs/show_bug.cgi?id=21148</a>). <span style="line-height:1.5;font-size:13.1999998092651px" class="">For this reason, we disabled indvar widening in NVPTX in </span><span style="line-height:1.5;font-size:13.1999998092651px" class=""><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__reviews.llvm.org_D6196&d=AwMFAg&c=8hUWFZcy2Z-Za5rBPlktOQ&r=Mfk2qtn1LTDThVkh6-oGglNfMADXfJdty4_bhmuhMHA&m=zeV6KKo_4QmNrl7a8HKbs0ceMMnzmsjyYtXh-iIkOjs&s=tBWMV2-ikpaxr-FHsNSadUWk0OWbNdw1pfBQUwutNAE&e=" class="">http://reviews.llvm.org/D6196</a>. </span><div class=""><span style="font-size:13.1999998092651px;line-height:1.5" class=""><br class=""></span></div><div class=""><span style="font-size:13.1999998092651px;line-height:1.5" class="">Hope it helps. </span></div></div></div></div></blockquote><div><br class=""></div><div>Hi Jingyue,</div><div><br class=""></div><div>But at the same time, if I understand correctly, you do want to LSR the address arithmetic (scale by 4 and the 64-bit addition to the base) into a 64-bit increment of 4. Correct?</div><div><br class=""></div><div>Adam</div><br class=""><blockquote type="cite" class=""><div class=""><div dir="ltr" class=""><div class=""><span style="font-size:13.1999998092651px;line-height:1.5" class=""><br class=""></span></div><div class=""><span style="font-size:13.1999998092651px;line-height:1.5" class="">Jingyue</span></div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Mon, Jun 29, 2015 at 11:59 AM Adam Nemet <<a href="mailto:anemet@apple.com" class="">anemet@apple.com</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br class="">
> On Jun 26, 2015, at 4:01 PM, Bjarke Roune <<a href="mailto:broune@google.com" target="_blank" class="">broune@google.com</a>> wrote:<br class="">
><br class="">
> *** Summary<br class="">
> I'd like to propose (and implement) functionality in LLVM to determine when a poison value from an instruction is guaranteed to produce undefined behavior. I want to use that to improve handling of nsw, inbounds etc. flags in scalar evolution and LSR. I imagine that there would be other uses for it. I'd like feedback on this idea before I proceed with it.<br class="">
><br class="">
><br class="">
> *** Details<br class="">
> Poison values do produce undefined behavior if the poison becomes externally observable. A load or store to a poison address value is externally observable and I'd like to use that in a simple analysis pass to derive guarantees that certain overflows would produce undefined behavior, not just poison.<br class="">
><br class="">
> Scalar evolution (and hence LSR) cannot currently make much use of the nsw and similar flags on instructions. That is because two instructions can map to the same scev even if one instruction has the nsw flag and the other one does not. If we applied the nsw flag to the scev, the scev for the instruction without the nsw flag would then incorrectly have the nsw flag.<br class="">
><br class="">
> Scalar evolution would be able to use the nsw flag from an instruction for recurrences when the loop header dominates the entire loop, the instruction with nsw post-dominates the loop header and undefined behavior is guaranteed on wrap via the poison value analysis pass that I'd like to write.<br class="">
><br class="">
> What do you think? Do we already have something similar to this?<br class="">
><br class="">
> Bjarke<br class="">
><br class="">
><br class="">
><br class="">
> *** PS: What got me thinking about this:<br class="">
> My immediate motivation is that I'd like LSR to be able to create induction variables for expressions like &ptr[i + offset] where i and offset are 32 bit integers, ptr is a loop-invariant 64 bit pointer, i is an induction variable and offset is loop-invariant. For that to happen, scalar evolution needs to propagate the nsw flag from i + offset to the scev so that it can transform<br class="">
><br class="">
> ((4 * (sext i32 {%offset,+,1}<nw><%loop> to i64))<nsw> + %ptr)<nsw><br class="">
><br class="">
> to<br class="">
><br class="">
> {((4 * (sext i32 %offset to i64)) + %ptr),+,4}<nsw><%loop><br class="">
<br class="">
I guess what I am missing here why indvars does not create an i64 induction variable for this?<br class="">
<br class="">
Adam<br class="">
<br class="">
<br class="">
><br class="">
> Currently the inner <nsw> is actually <nw>, which blocks the transformation (the outer two nsw's shouldn't currently be there either, as it's the same issue for inbounds on GEP: see llvm bug 23527)<br class="">
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