<div dir="ltr"><div>In my simulations, I am actually running the IR, rather than only evaluating cost function. I don't want to go too much into the details currently because I am hoping to get some results and publish them :)</div><div><br></div><div>I don't know if it will be useful for the LLVM codebase yet. If the weird IR proves to have useful application, then maybe that is possible.<br></div><div><div><div><div><div><br></div></div></div></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jun 17, 2015 at 2:10 PM, Renato Golin <span dir="ltr"><<a href="mailto:renato.golin@linaro.org" target="_blank">renato.golin@linaro.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On 17 June 2015 at 18:05, Matthias Braun <<a href="mailto:mbraun@apple.com">mbraun@apple.com</a>> wrote:<br>
> Having worked on SSA register allocators in the past I have to say that SSA is actually a good fit for register allocation. However LLVM IR is indeed not. You don't have any target instructions or register classed/constraints. It wouldn't make much sense to designate registers to llvm IR values nor is there a way to express that in IR. llvm has the machine instruction (MI) representation for that.<br>
<br>
</span>If I got it right, the intention here is to do simulations in IR. I'm<br>
assuming this is some form of cost function that instead of executing,<br>
would try to predict what would happen if it did run, without running.<br>
For that, doing some form of register allocation in IR can actually be<br>
beneficial from the register pressure point of view.<br>
<br>
You could even do that in a generic way by just passing the ABI<br>
register allocation first (what we do during lowering/legalization)<br>
and then just letting the simulator know how many GPRs there are, and<br>
the simulator can then estimate register pressure in basic blocks or<br>
functions by using a poor-man's version of liveness analysis on the<br>
remaining SSA registers in the sub-graph.<br>
<br>
While this would be an interesting project, I can't see this being an<br>
integral part of the LLVM codebase, as it would mess up the IR beyond<br>
recognition by current back-ends.<br>
<br>
cheers,<br>
--renato<br>
</blockquote></div><br></div>