<div dir="ltr">Thanks. I will also work on doing an SSA register allocation that returns SSA form (IR), since it is not yet implemented.<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jun 12, 2015 at 9:20 PM, Matthias Braun <span dir="ltr"><<a href="mailto:mbraun@apple.com" target="_blank">mbraun@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word"><div>llvm uses three different representations until machine code is emitted:</div><div><br></div><div>- the llvm language as specified in the llvm manuals, we usually call that IR</div><div>- the selection DAG</div><div>- machine code, which is often called MI</div><div><br></div><div>llvm currently only has infrastructure to serialize the first one. Register allocation only makes sense on the MI representation (before that we have no knowledge about register class or constraints, let alone which machine instructions will be used). Unfortunately MI cannot be serialized at the moment, although I think Alex Lorenz is currently working on adding this.</div><div><br></div><div>- Matthias</div><br><div><blockquote type="cite"><div><div class="h5"><div>On Jun 12, 2015, at 11:00 AM, kartikram3 <<a href="mailto:kartikram3@gmail.com" target="_blank">kartikram3@gmail.com</a>> wrote:</div><br></div></div><div><div><div class="h5"><div dir="ltr"><div><div><div><div><div><div><div><div><div><div><div><div><div><div><div>Hello all,<br> <br></div> I am trying to use the LLVM libraries to do register allocation on LLVM IR code -- and output IR as the result.<br></div>There are two problems that arise when we try this : <br><br></div>a. The LLVM backend requires that one goes through all the steps sequentially namely<br> <br></div> -- Instruction selection<br></div> -- Scheduling and Formation<br></div> -- SSA-based machine code optimizations<br></div> -- Register allocations <br><br><br> ...<br><br><br></div> -- Code emission<br><br></div>Is it possible to emit IR from the 1st 3 stages and then do register allocation on it ?<br></div>Normally, we would emit assembly based on the machine/ISA specifications during<br></div>instruction selection.<br><br></div>b. I have llvm IR in the form of a DAG already. This was obtained by using the llvm;;parseIRFile<br></div>function. I am not sure how to provide this ISA as an input to the backend phases as they<br></div>seem to accept all kinds of other objects. <br><br></div><div>Are there any llvm functions that accept a DAG as input so that we can do register allocation on it <br></div><div>subsequently ? <br><br><br></div><div>Note : This might look like a weird thing to do, but I want to do simulations on IR and getting a <br></div><div>register-allocated IR is useful for that purpose.<br></div></div>
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