<div dir="ltr">Hello, <div><br></div><div>I can see some fundamental differences between this work and my work. However, I think they are more complementary than "competitive". My work handles code extraction for offloading (in IR level) and offloading control with a runtime library this design is portable and not limited to openmp or another specific annotation scheme. It can handle different types of source code for offloading e.g. offloading of sequential code, parallel loops or even OpenCL kernels. </div><div><br></div><div>The runtime library is responsible for managing communication, coherency and scheduling. The library exposes a simple interface and the compiler generates calls to it. Plugins then provide support for the individual accelerator types. </div><div><br></div><div>The scheme you refer could be supported on the top of my infrastructure. I personally believe that code extraction and transformations for offloading should be done in IR and not in source level. The reason is that in IR level you have enough information about your program (e.g. datatypes) and a good idea about your target architectures. </div><div><br></div><div>--chris </div></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jun 8, 2015 at 4:27 AM, Sergey Ostanevich <span dir="ltr"><<a href="mailto:sergos.gnu@gmail.com" target="_blank">sergos.gnu@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Chirs,<br>
<br>
Have you seen an offloading infrastructure design proposal at<br>
<a href="http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-April/084986.html" target="_blank">http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-April/084986.html</a> ?<br>
It relies on the long-standing OpenMP standard with recent updates to<br>
support the heterogenous computations.<br>
Could you please review it and comment on how it fits to your needs?<br>
<br>
It's not quite clear from your proposal what source language standard<br>
do you plat to support - you just metion that OpenCL will be one of<br>
your backends, as far as I got it. What's your plan on sources -<br>
C/C++/FORTRAN?<br>
How would you control the offloading, data transfer, scheduling and so<br>
on? Whether it will be new language constructs, similar to prallel_for<br>
in Cilk Plus, or will it be pragma-based like in OpenMP or OpenACC?<br>
<br>
The design I mentioned above has an operable implementation fon NVIDIA<br>
target at the<br>
<br>
<a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_clang-2Domp_llvm-5Ftrunk&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=Mfk2qtn1LTDThVkh6-oGglNfMADXfJdty4_bhmuhMHA&m=LHFX3lSDb72WGXFwVkvTqVySGdePzZwOzC0MzgyDK5M&s=pC2tPUHfoHeFVRqVWaxUxeNxywzVbD6qOHbuk7G8V2o&e=" target="_blank">https://github.com/clang-omp/llvm_trunk</a><br>
<a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_clang-2Domp_clang-5Ftrunk&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=Mfk2qtn1LTDThVkh6-oGglNfMADXfJdty4_bhmuhMHA&m=LHFX3lSDb72WGXFwVkvTqVySGdePzZwOzC0MzgyDK5M&s=cT2DXQ4uTMGwQSBZKDhKkZHKvEkuf1dO60GCtSQTbaY&e=" target="_blank">https://github.com/clang-omp/clang_trunk</a><br>
<br>
with runtime implemented at<br>
<br>
<a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_clang-2Domp_libomptarget&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=Mfk2qtn1LTDThVkh6-oGglNfMADXfJdty4_bhmuhMHA&m=LHFX3lSDb72WGXFwVkvTqVySGdePzZwOzC0MzgyDK5M&s=zY-RGsYR3LhlPX59GMEpA91AaJjiDoQUy-LdrGPj1OI&e=" target="_blank">https://github.com/clang-omp/libomptarget</a><br>
<br>
you're welcome to try it out, if you have an appropriate device.<br>
<br>
Regards,<br>
Sergos<br>
<span class="im HOEnZb"><br>
On Sat, Jun 6, 2015 at 2:24 PM, Christos Margiolas<br>
<<a href="mailto:chrmargiolas@gmail.com">chrmargiolas@gmail.com</a>> wrote:<br>
</span><div class="HOEnZb"><div class="h5">> Hello,<br>
><br>
> Thank you a lot for the feedback. I believe that the heterogeneous engine<br>
> should be strongly connected with parallelization and vectorization efforts.<br>
> Most of the accelerators are parallel architectures where having efficient<br>
> parallelization and vectorization can be critical for performance.<br>
><br>
> I am interested in these efforts and I hope that my code can help you<br>
> managing the offloading operations. Your LLVM instruction set extensions may<br>
> require some changes in the analysis code but I think is going to be<br>
> straightforward.<br>
><br>
> I am planning to push my code on phabricator in the next days.<br>
><br>
> thanks,<br>
> Chris<br>
><br>
><br>
> On Fri, Jun 5, 2015 at 3:45 AM, Adve, Vikram Sadanand <<a href="mailto:vadve@illinois.edu">vadve@illinois.edu</a>><br>
> wrote:<br>
>><br>
>> Christos,<br>
>><br>
>> We would be very interested in learning more about this.<br>
>><br>
>> In my group, we (Prakalp Srivastava, Maria Kotsifakou and I) have been<br>
>> working on LLVM extensions to make it easier to target a wide range of<br>
>> accelerators in a heterogeneous mobile device, such as Qualcomm's Snapdragon<br>
>> and other APUs. Our approach has been to (a) add better abstractions of<br>
>> parallelism to the LLVM instruction set that can be mapped down to a wide<br>
>> range of parallel hardware accelerators; and (b) to develop optimizing<br>
>> "back-end" translators to generate efficient code for the accelerators from<br>
>> the extended IR.<br>
>><br>
>> So far, we have been targeting GPUs and vector hardware, but semi-custom<br>
>> (programmable) accelerators are our next goal. We have discussed DSPs as a<br>
>> valuable potential goal as well.<br>
>><br>
>> Judging from the brief information here, I'm guessing that our projects<br>
>> have been quite complementary. We have not worked on the extraction passes,<br>
>> scheduling, or other run-time components you mention and would be happy to<br>
>> use an existing solution for those. Our hope is that the IR extensions and<br>
>> translators will give your schedulers greater flexibility to retarget the<br>
>> extracted code components to different accelerators.<br>
>><br>
>> --Vikram S. Adve<br>
>> Visiting Professor, School of Computer and Communication Sciences, EPFL<br>
>> Professor, Department of Computer Science<br>
>> University of Illinois at Urbana-Champaign<br>
>> <a href="mailto:vadve@illinois.edu">vadve@illinois.edu</a><br>
>> <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=Mfk2qtn1LTDThVkh6-oGglNfMADXfJdty4_bhmuhMHA&m=LHFX3lSDb72WGXFwVkvTqVySGdePzZwOzC0MzgyDK5M&s=672gAZaRFZyo-tjzidFOM0QpioOWV7_OB7LBImhI16U&e=" target="_blank">http://llvm.org</a><br>
>><br>
>><br>
>><br>
>><br>
>> On Jun 5, 2015, at 3:18 AM, <a href="mailto:llvmdev-request@cs.uiuc.edu">llvmdev-request@cs.uiuc.edu</a> wrote:<br>
>><br>
>> > Date: Thu, 4 Jun 2015 17:35:25 -0700<br>
>> > From: Christos Margiolas <<a href="mailto:chrmargiolas@gmail.com">chrmargiolas@gmail.com</a>><br>
>> > To: LLVM Developers Mailing List <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>
>> > Subject: [LLVMdev] Supporting heterogeneous computing in llvm.<br>
>> > Message-ID:<br>
>> ><br>
>> > <<a href="mailto:CAC3KUCx0mpBrnrGjDVxQzxtBpnJXtw3herZ_E2pQoSqSyMNsKA@mail.gmail.com">CAC3KUCx0mpBrnrGjDVxQzxtBpnJXtw3herZ_E2pQoSqSyMNsKA@mail.gmail.com</a>><br>
>> > Content-Type: text/plain; charset="utf-8"<br>
>> ><br>
>> > Hello All,<br>
>> ><br>
>> > The last two months I have been working on the design and implementation<br>
>> > of<br>
>> > a heterogeneous execution engine for LLVM. I started this project as an<br>
>> > intern at the Qualcomm Innovation Center and I believe it can be useful<br>
>> > to<br>
>> > different people and use cases. I am planning to share more details and<br>
>> > a<br>
>> > set of patches in the next<br>
>> > days. However, I would first like to see if there is an interest for<br>
>> > this.<br>
>> ><br>
>> > The project is about providing compiler and runtime support for the<br>
>> > automatic and transparent offloading of loop or function workloads to<br>
>> > accelerators.<br>
>> ><br>
>> > It is composed of the following:<br>
>> > a) Compiler and Transformation Passes for extracting loops or functions<br>
>> > for<br>
>> > offloading.<br>
>> > b) A runtime library that handles scheduling, data sharing and coherency<br>
>> > between the<br>
>> > host and accelerator sides.<br>
>> > c) A modular codebase and design. Adaptors specialize the code<br>
>> > transformations for the target accelerators. Runtime plugins manage the<br>
>> > interaction with the different accelerator environments.<br>
>> ><br>
>> > So far, this work so far supports the Qualcomm DSP accelerator but I am<br>
>> > planning to extend it to support OpenCL accelerators. I have also<br>
>> > developed<br>
>> > a debug port where I can test the passes and the runtime without<br>
>> > requiring<br>
>> > an accelerator.<br>
>> ><br>
>> ><br>
>> > The project is still in early R&D stage and I am looking forward for<br>
>> > feedback and to gauge the interest level. I am willing to continue<br>
>> > working<br>
>> > on this as an open source project and bring it to the right shape so it<br>
>> > can<br>
>> > be merged with the LLVM tree.<br>
>> ><br>
>> ><br>
>> > Regards,<br>
>> > Chris<br>
>> ><br>
>> > P.S. I intent to join the llvm social in Bay Area tonight and I will be<br>
>> > more than happy to talk about it.<br>
>> > -------------- next part --------------<br>
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