<div dir="ltr">Hello,<div><br></div><div>Thank you a lot for the feedback. I believe that the heterogeneous engine should be strongly connected with parallelization and vectorization efforts. Most of the accelerators are parallel architectures where having efficient parallelization and vectorization can be critical for performance. </div><div><br></div><div>I am interested in these efforts and I hope that my code can help you managing the offloading operations. Your LLVM instruction set extensions may require some changes in the analysis code but I think is going to be straightforward.</div><div><br></div><div>I am planning to push my code on phabricator in the next days.</div><div><br></div><div>thanks,</div><div>Chris</div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jun 5, 2015 at 3:45 AM, Adve, Vikram Sadanand <span dir="ltr"><<a href="mailto:vadve@illinois.edu" target="_blank">vadve@illinois.edu</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Christos,<br>
<br>
We would be very interested in learning more about this.<br>
<br>
In my group, we (Prakalp Srivastava, Maria Kotsifakou and I) have been working on LLVM extensions to make it easier to target a wide range of accelerators in a heterogeneous mobile device, such as Qualcomm's Snapdragon and other APUs. Our approach has been to (a) add better abstractions of parallelism to the LLVM instruction set that can be mapped down to a wide range of parallel hardware accelerators; and (b) to develop optimizing "back-end" translators to generate efficient code for the accelerators from the extended IR.<br>
<br>
So far, we have been targeting GPUs and vector hardware, but semi-custom (programmable) accelerators are our next goal. We have discussed DSPs as a valuable potential goal as well.<br>
<br>
Judging from the brief information here, I'm guessing that our projects have been quite complementary. We have not worked on the extraction passes, scheduling, or other run-time components you mention and would be happy to use an existing solution for those. Our hope is that the IR extensions and translators will give your schedulers greater flexibility to retarget the extracted code components to different accelerators.<br>
<br>
--Vikram S. Adve<br>
Visiting Professor, School of Computer and Communication Sciences, EPFL<br>
Professor, Department of Computer Science<br>
University of Illinois at Urbana-Champaign<br>
<a href="mailto:vadve@illinois.edu">vadve@illinois.edu</a><br>
<a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=Mfk2qtn1LTDThVkh6-oGglNfMADXfJdty4_bhmuhMHA&m=3ZAVk127i3bp2CHIS2q18MT-0FbkppFPK8xcun3W3hw&s=SD_qYqB5CxjA76KRUHW2Gr7Llo43vfA79a36DQ6ynuQ&e=" target="_blank">http://llvm.org</a><br>
<br>
<br>
<br>
<br>
On Jun 5, 2015, at 3:18 AM, <a href="mailto:llvmdev-request@cs.uiuc.edu">llvmdev-request@cs.uiuc.edu</a> wrote:<br>
<br>
> Date: Thu, 4 Jun 2015 17:35:25 -0700<br>
> From: Christos Margiolas <<a href="mailto:chrmargiolas@gmail.com">chrmargiolas@gmail.com</a>><br>
> To: LLVM Developers Mailing List <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>
<span class="">> Subject: [LLVMdev] Supporting heterogeneous computing in llvm.<br>
</span>> Message-ID:<br>
> <<a href="mailto:CAC3KUCx0mpBrnrGjDVxQzxtBpnJXtw3herZ_E2pQoSqSyMNsKA@mail.gmail.com">CAC3KUCx0mpBrnrGjDVxQzxtBpnJXtw3herZ_E2pQoSqSyMNsKA@mail.gmail.com</a>><br>
> Content-Type: text/plain; charset="utf-8"<br>
<div><div class="h5">><br>
> Hello All,<br>
><br>
> The last two months I have been working on the design and implementation of<br>
> a heterogeneous execution engine for LLVM. I started this project as an<br>
> intern at the Qualcomm Innovation Center and I believe it can be useful to<br>
> different people and use cases. I am planning to share more details and a<br>
> set of patches in the next<br>
> days. However, I would first like to see if there is an interest for this.<br>
><br>
> The project is about providing compiler and runtime support for the<br>
> automatic and transparent offloading of loop or function workloads to<br>
> accelerators.<br>
><br>
> It is composed of the following:<br>
> a) Compiler and Transformation Passes for extracting loops or functions for<br>
> offloading.<br>
> b) A runtime library that handles scheduling, data sharing and coherency<br>
> between the<br>
> host and accelerator sides.<br>
> c) A modular codebase and design. Adaptors specialize the code<br>
> transformations for the target accelerators. Runtime plugins manage the<br>
> interaction with the different accelerator environments.<br>
><br>
> So far, this work so far supports the Qualcomm DSP accelerator but I am<br>
> planning to extend it to support OpenCL accelerators. I have also developed<br>
> a debug port where I can test the passes and the runtime without requiring<br>
> an accelerator.<br>
><br>
><br>
> The project is still in early R&D stage and I am looking forward for<br>
> feedback and to gauge the interest level. I am willing to continue working<br>
> on this as an open source project and bring it to the right shape so it can<br>
> be merged with the LLVM tree.<br>
><br>
><br>
> Regards,<br>
> Chris<br>
><br>
> P.S. I intent to join the llvm social in Bay Area tonight and I will be<br>
> more than happy to talk about it.<br>
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