<div dir="ltr"><div><span style="font-size:16px">Hi James,</span></div><div><span style="font-size:16px">Thanks for your prompt reply. I will add the pattern and send out for review.</span></div><div><span style="font-size:16px"><br></span></div><div><span style="font-size:16px">Thanks.</span></div><div><span style="font-size:16px">-Jyoti</span></div><div><br></div><div><span style="font-size:16px"><br></span></div><span style="font-size:16px">>Hi Jyoti,</span><br style="font-size:16px">><br style="font-size:16px"><span style="font-size:16px">>The first version doesn?t need a SMUL_LOHI, as it?s only doing a 32-bit multiply. The results of that 32-bit multiply are fed into the 64-bit ADD.</span><div>><br style="font-size:16px"><span style="font-size:16px">>The second one is doing a 64-bit multiply. This is expanded to a SMUL_LOHI, and is peepholed by ISelLowering.</span><br style="font-size:16px">><br style="font-size:16px"><span style="font-size:16px">>It looks simply like whoever wrote this peephole only considered that one version and didn?t consider the more canonical pattern (with a 32-bit multiply).</span><br style="font-size:16px">><br style="font-size:16px"><span style="font-size:16px">>The place to fix seems to be ARMISelLowering::7949 (AddCombineTo64BitMLAL) - adding a new pattern for that to detect.</span><br style="font-size:16px"><br><div><div><span style="font-size:16px">>Cheers,</span><br style="font-size:16px">><br style="font-size:16px"><span style="font-size:16px">>James</span><br></div></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, May 14, 2015 at 9:57 PM, <span dir="ltr"><<a href="mailto:llvmdev-request@cs.uiuc.edu" target="_blank">llvmdev-request@cs.uiuc.edu</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Send LLVMdev mailing list submissions to<br>
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Today's Topics:<br>
<br>
1. LLVM commit rights (OpenMP runtime) (Cownie, James H)<br>
2. Re: [Openmp-dev] LLVM commit rights (OpenMP runtime) (Hal Finkel)<br>
3. Re: RFC: Convergent attribute (Mehdi Amini)<br>
4. [ARM backend] SMLAL issue (Jyoti Rajendra Allur)<br>
5. Re: 3.6.1 -rc1 has been tagged. Testing begins. (Renato Golin)<br>
6. Re: RFC: Convergent attribute (Mehdi Amini)<br>
7. Re: [WinEH] A hiccup for the Windows C++ exception handling<br>
(Reid Kleckner)<br>
8. Re: [ARM backend] SMLAL issue (James Molloy)<br>
9. Re: RFC: ThinLTO Impementation Plan (Xinliang David Li)<br>
<br>
<br>
----------------------------------------------------------------------<br>
<br>
Message: 1<br>
Date: Thu, 14 May 2015 15:24:03 +0000<br>
From: "Cownie, James H" <<a href="mailto:james.h.cownie@intel.com">james.h.cownie@intel.com</a>><br>
To: LLVM Developers Mailing List <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>>,<br>
"<a href="mailto:openmp-dev@dcs-maillist2.engr.illinois.edu">openmp-dev@dcs-maillist2.engr.illinois.edu</a>"<br>
<<a href="mailto:openmp-dev@dcs-maillist2.engr.illinois.edu">openmp-dev@dcs-maillist2.engr.illinois.edu</a>><br>
Cc: "Peyton, Jonathan L" <<a href="mailto:jonathan.l.peyton@intel.com">jonathan.l.peyton@intel.com</a>><br>
Subject: [LLVMdev] LLVM commit rights (OpenMP runtime)<br>
Message-ID:<br>
<<a href="mailto:397D95928DECEF49983F5B237627E97841C62F0F@IRSMSX108.ger.corp.intel.com">397D95928DECEF49983F5B237627E97841C62F0F@IRSMSX108.ger.corp.intel.com</a>><br>
<br>
Content-Type: text/plain; charset="us-ascii"<br>
<br>
Hi All,<br>
<br>
I have been involved with the LLVM OpenMP runtime since it was first committed<br>
to the LLVM repository, and have LLVM commit rights. However, my role inside<br>
Intel is changing, and I believe that it therefore makes sense for someone else<br>
to have commit rights, and for mine to be revoked.<br>
<br>
I would therefore like to request that Johnny Peyton be given commit rights.<br>
He has been doing a lot of work on the LLVM OpenMP runtime (as can be seen in<br>
the mail chains), and if he had rights that would avoid some of the delays we've<br>
seen recently when Andrey has been out for Russian public holidays.<br>
<br>
I have really enjoyed working with the LLVM team, and will still be here, just with<br>
a less formal relationship inside Intel.<br>
<br>
-- Jim<br>
<br>
James Cownie <<a href="mailto:james.h.cownie@intel.com">james.h.cownie@intel.com</a>><br>
SSG/DPD/TCAR (Technical Computing, Analyzers and Runtimes)<br>
Tel: +44 117 9071438<br>
<br>
---------------------------------------------------------------------<br>
Intel Corporation (UK) Limited<br>
Registered No. 1134945 (England)<br>
Registered Office: Pipers Way, Swindon SN3 1RJ<br>
VAT No: 860 2173 47<br>
<br>
This e-mail and any attachments may contain confidential material for<br>
the sole use of the intended recipient(s). Any review or distribution<br>
by others is strictly prohibited. If you are not the intended<br>
recipient, please contact the sender and delete all copies.<br>
<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 2<br>
Date: Thu, 14 May 2015 10:32:13 -0500<br>
From: Hal Finkel <<a href="mailto:hfinkel@anl.gov">hfinkel@anl.gov</a>><br>
To: James H Cownie <<a href="mailto:james.h.cownie@intel.com">james.h.cownie@intel.com</a>><br>
Cc: <a href="mailto:openmp-dev@dcs-maillist2.engr.illinois.edu">openmp-dev@dcs-maillist2.engr.illinois.edu</a>, LLVM Developers<br>
Mailing List <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>
Subject: Re: [LLVMdev] [Openmp-dev] LLVM commit rights (OpenMP<br>
runtime)<br>
Message-ID:<br>
<4797056.576.1431617533573.JavaMail.javamailuser@localhost><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
----- Original Message -----<br>
> From: "James H Cownie" <<a href="mailto:james.h.cownie@intel.com">james.h.cownie@intel.com</a>><br>
> To: "LLVM Developers Mailing List" <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>>, <a href="mailto:openmp-dev@dcs-maillist2.engr.illinois.edu">openmp-dev@dcs-maillist2.engr.illinois.edu</a><br>
> Sent: Thursday, May 14, 2015 10:24:03 AM<br>
> Subject: [Openmp-dev] LLVM commit rights (OpenMP runtime)<br>
><br>
> Hi All,<br>
><br>
> I have been involved with the LLVM OpenMP runtime since it was first<br>
> committed<br>
> to the LLVM repository, and have LLVM commit rights. However, my role<br>
> inside<br>
> Intel is changing, and I believe that it therefore makes sense for<br>
> someone else<br>
> to have commit rights, and for mine to be revoked.<br>
><br>
> I would therefore like to request that Johnny Peyton be given commit<br>
<br>
Johnny has been a regular contributor, he simply needs to submit a request for commit access as documented here:<br>
<a href="http://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access" target="_blank">http://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access</a><br>
<br>
> rights.<br>
> He has been doing a lot of work on the LLVM OpenMP runtime (as can be<br>
> seen in<br>
> the mail chains), and if he had rights that would avoid some of the<br>
> delays we've<br>
> seen recently when Andrey has been out for Russian public holidays.<br>
><br>
> I have really enjoyed working with the LLVM team, and will still be<br>
> here, just with<br>
> a less formal relationship inside Intel.<br>
<br>
You've made a valuable contribution to the LLVM project, and I wish you the best of luck with your future projects. I hope you'll stick around on the mailing lists to provide advice and opinions.<br>
<br>
-Hal<br>
<br>
><br>
> -- Jim<br>
><br>
> James Cownie <<a href="mailto:james.h.cownie@intel.com">james.h.cownie@intel.com</a>><br>
> SSG/DPD/TCAR (Technical Computing, Analyzers and Runtimes)<br>
> Tel: +44 117 9071438<br>
><br>
> ---------------------------------------------------------------------<br>
> Intel Corporation (UK) Limited<br>
> Registered No. 1134945 (England)<br>
> Registered Office: Pipers Way, Swindon SN3 1RJ<br>
> VAT No: 860 2173 47<br>
><br>
> This e-mail and any attachments may contain confidential material for<br>
> the sole use of the intended recipient(s). Any review or distribution<br>
> by others is strictly prohibited. If you are not the intended<br>
> recipient, please contact the sender and delete all copies.<br>
><br>
><br>
> _______________________________________________<br>
> Openmp-dev mailing list<br>
> <a href="mailto:Openmp-dev@dcs-maillist2.engr.illinois.edu">Openmp-dev@dcs-maillist2.engr.illinois.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/openmp-dev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/openmp-dev</a><br>
><br>
<br>
--<br>
Hal Finkel<br>
Assistant Computational Scientist<br>
Leadership Computing Facility<br>
Argonne National Laboratory<br>
<br>
<br>
------------------------------<br>
<br>
Message: 3<br>
Date: Thu, 14 May 2015 08:33:32 -0700<br>
From: Mehdi Amini <<a href="mailto:mehdi.amini@apple.com">mehdi.amini@apple.com</a>><br>
To: Philip Reames <<a href="mailto:listmail@philipreames.com">listmail@philipreames.com</a>><br>
Cc: Lista LLVM-dev <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>
Subject: Re: [LLVMdev] RFC: Convergent attribute<br>
Message-ID: <<a href="mailto:7B862523-9330-4F84-9011-DB0FF8830ADD@apple.com">7B862523-9330-4F84-9011-DB0FF8830ADD@apple.com</a>><br>
Content-Type: text/plain; charset=utf-8<br>
<br>
<br>
> On May 13, 2015, at 6:00 PM, Philip Reames <<a href="mailto:listmail@philipreames.com">listmail@philipreames.com</a>> wrote:<br>
><br>
> LGTM. Please put pretty much everything in this email into a documentation page. Doesn't have to be LangRef, but definitely something linked from there.<br>
><br>
> Also, it would be good to explicitly say that this is working around a limitation in the register allocator. Just because it's a limitation which would be very hard to address doesn't mean it isn't a limitation. :)<br>
<br>
Only a subset of the problem (architecture specific) can be addressed by a ?clever? register allocator I think. The general problem goes beyond.<br>
<br>
?<br>
Mehdi<br>
<br>
><br>
> Philip<br>
><br>
> On 05/13/2015 01:17 PM, Owen Anderson wrote:<br>
>> Below is a proposal for a new "convergent" intrinsic attribute and MachineInstr property, needed for correctly modeling many SPMD/SIMT programming models in LLVM. Comments and feedback welcome.<br>
>><br>
>> ?Owen<br>
>><br>
>><br>
>><br>
>><br>
>><br>
>> In order to make LLVM more suitable for programming models variously called SPMD<br>
>> and SIMT, we would like to propose a new intrinsic and MachineInstr annotation<br>
>> called "convergent", which will be used to impose certain control flow and/or<br>
>> code motion constraints that are necessary for the correct compilation of some<br>
>> common constructs in these programming models.<br>
>><br>
>> Our proposal strives to define the semantics of these annotations *without*<br>
>> introducing a definition of SPMD/SIMT programming models into LLVM IR. Rather,<br>
>> the properties that must be preserved are specified purely in terms of single<br>
>> thread semantics. This allows pass authors to reason about the constraints<br>
>> without having to consider alternative programming models. The downside to<br>
>> this approach is that the motivation and necessity of these constraints in not<br>
>> easily understood without understanding the programming model from which they<br>
>> derive.<br>
>><br>
>> *** WHAT ***<br>
>><br>
>> (Thanks to Phil Reames for input on this definition.)<br>
>><br>
>> An operation marked convergent may be transformed or moved within the program<br>
>> if and only the post-transform placement of the convergent operation is<br>
>> control equivalent (A dominated B, B post-dominates A, or vice-versa) to<br>
>> its original position.<br>
>><br>
>> This definition is overly strict with respect to some SPMD/SIMT models,<br>
>> but cannot be relaxed without introducing a specific model into LLVM IR. We<br>
>> believe it is important for LLVM itself to remain agnostic to any specific<br>
>> model. This allows core passes to preserve correctness for stricter models,<br>
>> while more relaxed models can implement additional transforms that use<br>
>> weaker constraints on top of core LLVM.<br>
>><br>
>> *** HOW ***<br>
>><br>
>> Once the attribute has been added, we anticipate the following changes to<br>
>> optimization passes will be required:<br>
>> - Restrict Sink and MachineSink for convergent operations<br>
>> - Disabling PRE for convergent operations<br>
>> - Disabling jump threading of convergent operations<br>
>> - Auditing SimplifyCFG for additional transforms that break convergent guarantees<br>
>><br>
>> *** WHY ***<br>
>><br>
>> SPMD/SIMT programming models are a family of related programming models in<br>
>> which multiple threads execute in a per-instruction lockstep fashion.<br>
>> Predication is typically used to implement acyclic control flow that would<br>
>> otherwise diverge the PC address of the lockstep threads.<br>
>><br>
>> In these models, each thread's register set is typically indepedent, but there<br>
>> exist a small number of important circumstances in which a thread may access<br>
>> register storage from one of its lockstep neighbors. Examples include gradient<br>
>> computation for texture lookups, as well a cross-thread broadcast and shuffle<br>
>> operations.<br>
>><br>
>> These operations that provide access to another thread's register storage pose<br>
>> a particular challenge to the compiler, particularly when combined with the<br>
>> use of predication for control flow. Consider the following example:<br>
>><br>
>> // texture lookup that computes gradient of r0, last use of r0<br>
>> r1 = texture2D(..., r0, ...)<br>
>> if (...) {<br>
>> // r0 used as temporary here<br>
>> r0 = ...<br>
>> r2 = r0 + ...<br>
>> } else {<br>
>> // only use of r1<br>
>> r2 = r1 + ...<br>
>> }<br>
>><br>
>> In this example, various optimizations might try to sink the texture2D operation<br>
>> into the else block, like so:<br>
>><br>
>> if (...) {<br>
>> r0 = ...<br>
>> r2 = r0 + ...<br>
>> } else {<br>
>> r1 = texture2D(..., r0, ...)<br>
>> r2 = r1 + ...<br>
>> }<br>
>><br>
>> At this point, it starts to become clear that a problem can occur when two<br>
>> neighbor threads want to take different paths through the if-else construct.<br>
>> Logically, the thread that wishes to execute the texture2D races with its<br>
>> neighbor to reads the neighbor's value of r0 before it gets overridden.<br>
>><br>
>> In most SPMD/SIMT implementations, the fallout of this races is exposed via<br>
>> the predicated expression of acyclic control flow:<br>
>><br>
>> pred0 <- cmp ...<br>
>> if (pred0) r0 = ...<br>
>> if (pred0) r2 = r0 + ...<br>
>> if (!pred0) r1 = texture2D(..., r0, ...)<br>
>> if (!pred0) r2 = r1 + ...<br>
>><br>
>> If thread 0 takes the else path and perform the texture2D operation, but<br>
>> its neighbor thread 1 takes the then branch, then the texture2D will fail<br>
>> because thread 1 has already overwritten its value of r0 before thread 0 has<br>
>> a chance to read it.<br>
>><br>
>><br>
>><br>
>> _______________________________________________<br>
>> LLVM Developers mailing list<br>
>> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
><br>
><br>
> _______________________________________________<br>
> LLVM Developers mailing list<br>
> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 4<br>
Date: Thu, 14 May 2015 15:36:33 +0000 (GMT)<br>
From: Jyoti Rajendra Allur <<a href="mailto:jyoti.allur@samsung.com">jyoti.allur@samsung.com</a>><br>
To: <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>, <a href="mailto:t.p.northover@gmail.com">t.p.northover@gmail.com</a>, <a href="mailto:james.molloy@arm.com">james.molloy@arm.com</a><br>
Subject: [LLVMdev] [ARM backend] SMLAL issue<br>
Message-ID:<br>
<1106717447.198031431617793195.JavaMail.weblogic@ep2mlwas08b><br>
Content-Type: text/plain; charset=windows-1252<br>
<br>
Hi Tim/James,<br>
In the following code, MUL, ADDS, ADC are combined to SMLAL only if 'b' and 'c' are promoted to long long type during multiplication. Shouldn't they be allowed to be combined to SMLAL<br>
even in the code as is without promoting b and c to long long type?<br>
<br>
I found the reason for not combining to SMAL to be this, ADDS operand 0 has opcode not set as ISD::SMUL_LOHI even though operand 0 ie., R2 is a result of SMULBB as seen in the assembly.<br>
<br>
long long<br>
foo (long long a, int b, int c)<br>
{<br>
return a + b * c; ===> return a + (long long)b * (long long)c;<br>
<br>
}<br>
ldrb r2, [r2]<br>
ldrb r3, [r3]<br>
smulbb r2, r3, r2<br>
adds r0, r2, r0<br>
adc r1, r1, #0<br>
bx lr<br>
<br>
I have already checked in combine function in DAG combiner and visitADDC, ADDS node operand0 's opcode is not set to ISD::SMUL_LOHI. Only when b and c are typecasted to long long, operand0 opcode is set to ISD::SMUL_LOHI<br>
Is this a likely bug, if not is there a specific reason for designing it this way ?<br>
<br>
<br>
Regards,<br>
Jyoti Allur<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 5<br>
Date: Thu, 14 May 2015 16:49:56 +0100<br>
From: Renato Golin <<a href="mailto:renato.golin@linaro.org">renato.golin@linaro.org</a>><br>
To: Tom Stellard <<a href="mailto:tom@stellard.net">tom@stellard.net</a>><br>
Cc: Clang Dev <<a href="mailto:cfe-dev@cs.uiuc.edu">cfe-dev@cs.uiuc.edu</a>>, LLVM Dev <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>
Subject: Re: [LLVMdev] 3.6.1 -rc1 has been tagged. Testing begins.<br>
Message-ID:<br>
<<a href="mailto:CAMSE1kdv8O7HSBxLZMtddyiYZwxzPh7BZDJ3qTufu0W39MkkUQ@mail.gmail.com">CAMSE1kdv8O7HSBxLZMtddyiYZwxzPh7BZDJ3qTufu0W39MkkUQ@mail.gmail.com</a>><br>
Content-Type: text/plain; charset=UTF-8<br>
<br>
On 13 May 2015 at 18:47, Renato Golin <<a href="mailto:renato.golin@linaro.org">renato.golin@linaro.org</a>> wrote:<br>
> The binary was uploaded into the server, in case someone wants to have<br>
> a look, but I'll have to fix my environment for the final release.<br>
<br>
So, I've uploaded a new binary, built with a stable Debian, GCC 4.9.2, etc.<br>
<br>
I'm seeing two execution failures in the test-suite:<br>
<br>
MultiSource/Benchmarks/MiBench/consumer-typeset/consumer-typeset<br>
MultiSource/UnitTests/C++11/frame_layout/frame_layout<br>
<br>
Investigating...<br>
<br>
cheers,<br>
--renato<br>
<br>
<br>
------------------------------<br>
<br>
Message: 6<br>
Date: Thu, 14 May 2015 08:50:49 -0700<br>
From: Mehdi Amini <<a href="mailto:mehdi.amini@apple.com">mehdi.amini@apple.com</a>><br>
To: Philip Reames <<a href="mailto:listmail@philipreames.com">listmail@philipreames.com</a>><br>
Cc: Lista LLVM-dev <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>
Subject: Re: [LLVMdev] RFC: Convergent attribute<br>
Message-ID: <<a href="mailto:5AEA9F2F-14DE-4063-AFBC-1E67061DE160@apple.com">5AEA9F2F-14DE-4063-AFBC-1E67061DE160@apple.com</a>><br>
Content-Type: text/plain; charset=utf-8<br>
<br>
<br>
> On May 14, 2015, at 8:33 AM, Mehdi Amini <<a href="mailto:mehdi.amini@apple.com">mehdi.amini@apple.com</a>> wrote:<br>
><br>
>><br>
>> On May 13, 2015, at 6:00 PM, Philip Reames <<a href="mailto:listmail@philipreames.com">listmail@philipreames.com</a>> wrote:<br>
>><br>
>> LGTM. Please put pretty much everything in this email into a documentation page. Doesn't have to be LangRef, but definitely something linked from there.<br>
>><br>
>> Also, it would be good to explicitly say that this is working around a limitation in the register allocator. Just because it's a limitation which would be very hard to address doesn't mean it isn't a limitation. :)<br>
><br>
> Only a subset of the problem (architecture specific) can be addressed by a ?clever? register allocator I think. The general problem goes beyond.<br>
<br>
Thinking more about it, the example I had in mind was wrong and I can?t find one right now, I retract what I said :)<br>
<br>
?<br>
Mehdi<br>
<br>
<br>
>><br>
>> Philip<br>
>><br>
>> On 05/13/2015 01:17 PM, Owen Anderson wrote:<br>
>>> Below is a proposal for a new "convergent" intrinsic attribute and MachineInstr property, needed for correctly modeling many SPMD/SIMT programming models in LLVM. Comments and feedback welcome.<br>
>>><br>
>>> ?Owen<br>
>>><br>
>>><br>
>>><br>
>>><br>
>>><br>
>>> In order to make LLVM more suitable for programming models variously called SPMD<br>
>>> and SIMT, we would like to propose a new intrinsic and MachineInstr annotation<br>
>>> called "convergent", which will be used to impose certain control flow and/or<br>
>>> code motion constraints that are necessary for the correct compilation of some<br>
>>> common constructs in these programming models.<br>
>>><br>
>>> Our proposal strives to define the semantics of these annotations *without*<br>
>>> introducing a definition of SPMD/SIMT programming models into LLVM IR. Rather,<br>
>>> the properties that must be preserved are specified purely in terms of single<br>
>>> thread semantics. This allows pass authors to reason about the constraints<br>
>>> without having to consider alternative programming models. The downside to<br>
>>> this approach is that the motivation and necessity of these constraints in not<br>
>>> easily understood without understanding the programming model from which they<br>
>>> derive.<br>
>>><br>
>>> *** WHAT ***<br>
>>><br>
>>> (Thanks to Phil Reames for input on this definition.)<br>
>>><br>
>>> An operation marked convergent may be transformed or moved within the program<br>
>>> if and only the post-transform placement of the convergent operation is<br>
>>> control equivalent (A dominated B, B post-dominates A, or vice-versa) to<br>
>>> its original position.<br>
>>><br>
>>> This definition is overly strict with respect to some SPMD/SIMT models,<br>
>>> but cannot be relaxed without introducing a specific model into LLVM IR. We<br>
>>> believe it is important for LLVM itself to remain agnostic to any specific<br>
>>> model. This allows core passes to preserve correctness for stricter models,<br>
>>> while more relaxed models can implement additional transforms that use<br>
>>> weaker constraints on top of core LLVM.<br>
>>><br>
>>> *** HOW ***<br>
>>><br>
>>> Once the attribute has been added, we anticipate the following changes to<br>
>>> optimization passes will be required:<br>
>>> - Restrict Sink and MachineSink for convergent operations<br>
>>> - Disabling PRE for convergent operations<br>
>>> - Disabling jump threading of convergent operations<br>
>>> - Auditing SimplifyCFG for additional transforms that break convergent guarantees<br>
>>><br>
>>> *** WHY ***<br>
>>><br>
>>> SPMD/SIMT programming models are a family of related programming models in<br>
>>> which multiple threads execute in a per-instruction lockstep fashion.<br>
>>> Predication is typically used to implement acyclic control flow that would<br>
>>> otherwise diverge the PC address of the lockstep threads.<br>
>>><br>
>>> In these models, each thread's register set is typically indepedent, but there<br>
>>> exist a small number of important circumstances in which a thread may access<br>
>>> register storage from one of its lockstep neighbors. Examples include gradient<br>
>>> computation for texture lookups, as well a cross-thread broadcast and shuffle<br>
>>> operations.<br>
>>><br>
>>> These operations that provide access to another thread's register storage pose<br>
>>> a particular challenge to the compiler, particularly when combined with the<br>
>>> use of predication for control flow. Consider the following example:<br>
>>><br>
>>> // texture lookup that computes gradient of r0, last use of r0<br>
>>> r1 = texture2D(..., r0, ...)<br>
>>> if (...) {<br>
>>> // r0 used as temporary here<br>
>>> r0 = ...<br>
>>> r2 = r0 + ...<br>
>>> } else {<br>
>>> // only use of r1<br>
>>> r2 = r1 + ...<br>
>>> }<br>
>>><br>
>>> In this example, various optimizations might try to sink the texture2D operation<br>
>>> into the else block, like so:<br>
>>><br>
>>> if (...) {<br>
>>> r0 = ...<br>
>>> r2 = r0 + ...<br>
>>> } else {<br>
>>> r1 = texture2D(..., r0, ...)<br>
>>> r2 = r1 + ...<br>
>>> }<br>
>>><br>
>>> At this point, it starts to become clear that a problem can occur when two<br>
>>> neighbor threads want to take different paths through the if-else construct.<br>
>>> Logically, the thread that wishes to execute the texture2D races with its<br>
>>> neighbor to reads the neighbor's value of r0 before it gets overridden.<br>
>>><br>
>>> In most SPMD/SIMT implementations, the fallout of this races is exposed via<br>
>>> the predicated expression of acyclic control flow:<br>
>>><br>
>>> pred0 <- cmp ...<br>
>>> if (pred0) r0 = ...<br>
>>> if (pred0) r2 = r0 + ...<br>
>>> if (!pred0) r1 = texture2D(..., r0, ...)<br>
>>> if (!pred0) r2 = r1 + ...<br>
>>><br>
>>> If thread 0 takes the else path and perform the texture2D operation, but<br>
>>> its neighbor thread 1 takes the then branch, then the texture2D will fail<br>
>>> because thread 1 has already overwritten its value of r0 before thread 0 has<br>
>>> a chance to read it.<br>
>>><br>
>>><br>
>>><br>
>>> _______________________________________________<br>
>>> LLVM Developers mailing list<br>
>>> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
>>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
>><br>
>><br>
>> _______________________________________________<br>
>> LLVM Developers mailing list<br>
>> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
><br>
><br>
> _______________________________________________<br>
> LLVM Developers mailing list<br>
> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
<br>
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------------------------------<br>
<br>
Message: 7<br>
Date: Thu, 14 May 2015 09:12:10 -0700<br>
From: Reid Kleckner <<a href="mailto:rnk@google.com">rnk@google.com</a>><br>
To: "Kaylor, Andrew" <<a href="mailto:andrew.kaylor@intel.com">andrew.kaylor@intel.com</a>><br>
Cc: LLVM Developers Mailing List <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>
Subject: Re: [LLVMdev] [WinEH] A hiccup for the Windows C++ exception<br>
handling<br>
Message-ID:<br>
<CACs=tyKxsnELWEz=-<a href="mailto:EMKaBqc0Uw-yXxxwE6BB4BdNP2GMyf3jw@mail.gmail.com">EMKaBqc0Uw-yXxxwE6BB4BdNP2GMyf3jw@mail.gmail.com</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
On Wed, May 13, 2015 at 4:37 PM, Kaylor, Andrew <<a href="mailto:andrew.kaylor@intel.com">andrew.kaylor@intel.com</a>><br>
wrote:<br>
<br>
> I made some progress this afternoon. I now have a set of changes in my<br>
> local sandbox that allows clang to pass all of the tests in the suite I?ve<br>
> been using to exercise this code.<br>
><br>
><br>
><br>
> How do you feel about working these changes into trunk to establish a<br>
> working baseline, even knowing that parts of this are going to be<br>
> redesigned?<br>
><br>
<br>
I guess I'm kind of ambivalent about continuing in the current direction.<br>
It doesn't hurt, but if it provides someone with basic functionality for<br>
now, then that's OK. On the other hand, the tests won't be particularly<br>
valuable because Clang is going to emit new LLVM IR, so they'll need to be<br>
redone.<br>
<br>
I also think that, given that the rewrite will take at least a month, we<br>
should turn MSVC C++ exceptions off by default in Clang until it's ready.<br>
We need some hidden flag that isn't /EHs. I'm already tired of getting bug<br>
reports along the lines of "clang crashed while compiling MSVC-style<br>
exceptions". Of course, the user can't tell from the crash that the<br>
workaround is just "turn off exceptions until they work". =/<br>
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<br>
Message: 8<br>
Date: Thu, 14 May 2015 17:16:01 +0100<br>
From: James Molloy <<a href="mailto:James.Molloy@arm.com">James.Molloy@arm.com</a>><br>
To: "<a href="mailto:jyoti.allur@samsung.com">jyoti.allur@samsung.com</a>" <<a href="mailto:jyoti.allur@samsung.com">jyoti.allur@samsung.com</a>><br>
Cc: "<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>" <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>
Subject: Re: [LLVMdev] [ARM backend] SMLAL issue<br>
Message-ID: <<a href="mailto:A629EA4C-18FA-4670-AFD8-B065E8C291D9@arm.com">A629EA4C-18FA-4670-AFD8-B065E8C291D9@arm.com</a>><br>
Content-Type: text/plain; charset=WINDOWS-1252<br>
<br>
Hi Jyoti,<br>
<br>
The first version doesn?t need a SMUL_LOHI, as it?s only doing a 32-bit multiply. The results of that 32-bit multiply are fed into the 64-bit ADD.<br>
<br>
The second one is doing a 64-bit multiply. This is expanded to a SMUL_LOHI, and is peepholed by ISelLowering.<br>
<br>
It looks simply like whoever wrote this peephole only considered that one version and didn?t consider the more canonical pattern (with a 32-bit multiply).<br>
<br>
The place to fix seems to be ARMISelLowering::7949 (AddCombineTo64BitMLAL) - adding a new pattern for that to detect.<br>
<br>
Cheers,<br>
<br>
James<br>
<br>
On 14 May 2015, at 16:36, Jyoti Rajendra Allur <<a href="mailto:jyoti.allur@samsung.com">jyoti.allur@samsung.com</a>> wrote:<br>
<br>
> Hi Tim/James,<br>
> In the following code, MUL, ADDS, ADC are combined to SMLAL only if 'b' and 'c' are promoted to long long type during multiplication. Shouldn't they be allowed to be combined to SMLAL<br>
> even in the code as is without promoting b and c to long long type?<br>
><br>
> I found the reason for not combining to SMAL to be this, ADDS operand 0 has opcode not set as ISD::SMUL_LOHI even though operand 0 ie., R2 is a result of SMULBB as seen in the assembly.<br>
><br>
> long long<br>
> foo (long long a, int b, int c)<br>
> {<br>
> return a + b * c; ===> return a + (long long)b * (long long)c;<br>
><br>
> }<br>
> ldrb r2, [r2]<br>
> ldrb r3, [r3]<br>
> smulbb r2, r3, r2<br>
> adds r0, r2, r0<br>
> adc r1, r1, #0<br>
> bx lr<br>
><br>
> I have already checked in combine function in DAG combiner and visitADDC, ADDS node operand0 's opcode is not set to ISD::SMUL_LOHI. Only when b and c are typecasted to long long, operand0 opcode is set to ISD::SMUL_LOHI<br>
> Is this a likely bug, if not is there a specific reason for designing it this way ?<br>
><br>
><br>
> Regards,<br>
> Jyoti Allur<br>
<br>
<br>
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------------------------------<br>
<br>
Message: 9<br>
Date: Thu, 14 May 2015 09:26:53 -0700<br>
From: Xinliang David Li <<a href="mailto:xinliangli@gmail.com">xinliangli@gmail.com</a>><br>
To: Teresa Johnson <<a href="mailto:tejohnson@google.com">tejohnson@google.com</a>><br>
Cc: "<<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>> List" <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>
Subject: Re: [LLVMdev] RFC: ThinLTO Impementation Plan<br>
Message-ID:<br>
<<a href="mailto:CALRgJCNmJrvxArwGBKgnVDuh81jZep1QbLQ9T_XjN9cgYJxs7A@mail.gmail.com">CALRgJCNmJrvxArwGBKgnVDuh81jZep1QbLQ9T_XjN9cgYJxs7A@mail.gmail.com</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
The design objective is to make thinLTO mostly transparent to binutil tools<br>
to enable easy integration with any build system in the wild.<br>
'Pass-through' mode with 'ld -r' instead of the partial LTO mode is<br>
another reason.<br>
<br>
David<br>
<br>
On Thu, May 14, 2015 at 7:30 AM, Teresa Johnson <<a href="mailto:tejohnson@google.com">tejohnson@google.com</a>><br>
wrote:<br>
<br>
> On Thu, May 14, 2015 at 7:22 AM, Eric Christopher <<a href="mailto:echristo@gmail.com">echristo@gmail.com</a>><br>
> wrote:<br>
> > So, what Alex is saying is that we have these tools as well and they<br>
> > understand bitcode just fine, as well as every object format - not just<br>
> ELF.<br>
> > :)<br>
><br>
> Right, there are also LLVM specific versions (llvm-ar, llvm-nm) that<br>
> handle bitcode similarly to the way the standard tool + plugin does.<br>
> But the goal we are trying to achieve is to allow the standard system<br>
> versions of the tools to handle these files without requiring a<br>
> plugin. I know the LLVM tool handles other object formats, but I'm not<br>
> sure how that helps here? We're not planning to replace those tools,<br>
> just allow the standard system versions to handle the intermediate<br>
> objects produced by ThinLTO.<br>
><br>
> Thanks,<br>
> Teresa<br>
><br>
> ><br>
> > -eric<br>
> ><br>
> ><br>
> > On Thu, May 14, 2015, 6:55 AM Teresa Johnson <<a href="mailto:tejohnson@google.com">tejohnson@google.com</a>><br>
> wrote:<br>
> >><br>
> >> On Wed, May 13, 2015 at 11:23 PM, Xinliang David Li<br>
> >> <<a href="mailto:xinliangli@gmail.com">xinliangli@gmail.com</a>> wrote:<br>
> >> ><br>
> >> ><br>
> >> > On Wed, May 13, 2015 at 10:46 PM, Alex Rosenberg <<a href="mailto:alexr@leftfield.org">alexr@leftfield.org</a><br>
> ><br>
> >> > wrote:<br>
> >> >><br>
> >> >> "ELF-wrapped bitcode" seems potentially controversial to me.<br>
> >> >><br>
> >> >> What about ar, nm, and various ld implementations adds this<br>
> >> >> requirement?<br>
> >> >> What about the LLVM implementations of these tools is lacking?<br>
> >> ><br>
> >> ><br>
> >> > Sorry I can not parse your questions properly. Can you make it<br>
> clearer?<br>
> >><br>
> >> Alex is asking what the issue is with ar, nm, ld -r and regular<br>
> >> bitcode that makes using elf-wrapped bitcode easier.<br>
> >><br>
> >> The issue is that generally you need to provide a plugin to these<br>
> >> tools in order for them to understand and handle bitcode files. We'd<br>
> >> like standard tools to work without requiring a plugin as much as<br>
> >> possible. And in some cases we want them to be handled different than<br>
> >> the way bitcode files are handled with the plugin.<br>
> >><br>
> >> nm: Without a plugin, normal bitcode files are inscrutable. When<br>
> >> provided the gold plugin it can emit the symbols.<br>
> >><br>
> >> ar: Without a plugin, it will create an archive of bitcode files, but<br>
> >> without an index, so it can't be handled by the linker even with a<br>
> >> plugin on an -flto link. When ar is provided the gold plugin it does<br>
> >> create an index, so the linker + gold plugin handle it appropriately<br>
> >> on an -flto link.<br>
> >><br>
> >> ld -r: Without a plugin, fails when provided bitcode inputs. When<br>
> >> provided the gold plugin, it handles them but compiles them all the<br>
> >> way through to ELF executable instructions via a partial LTO link.<br>
> >> This is where we would like to differ in behavior (while also not<br>
> >> requiring a plugin) with ELF-wrapped bitcode: we would like the ld -r<br>
> >> output file to still contain ELF-wrapped bitcode, delaying the LTO<br>
> >> until the full link step.<br>
> >><br>
> >> Let me know if that helps address your concerns.<br>
> >><br>
> >> Thanks,<br>
> >> Teresa<br>
> >><br>
> >> ><br>
> >> > David<br>
> >> ><br>
> >> >><br>
> >> >><br>
> >> >> Alex<br>
> >> >><br>
> >> >> > On May 13, 2015, at 7:44 PM, Teresa Johnson <<a href="mailto:tejohnson@google.com">tejohnson@google.com</a>><br>
> >> >> > wrote:<br>
> >> >> ><br>
> >> >> > I've included below an RFC for implementing ThinLTO in LLVM,<br>
> looking<br>
> >> >> > forward to feedback and questions.<br>
> >> >> > Thanks!<br>
> >> >> > Teresa<br>
> >> >> ><br>
> >> >> ><br>
> >> >> ><br>
> >> >> > RFC to discuss plans for implementing ThinLTO upstream. Background<br>
> >> >> > can<br>
> >> >> > be found in slides from EuroLLVM 2015:<br>
> >> >> ><br>
> >> >> ><br>
> >> >> ><br>
> <a href="https://drive.google.com/open?id=0B036uwnWM6RWWER1ZEl5SUNENjQ&authuser=0" target="_blank">https://drive.google.com/open?id=0B036uwnWM6RWWER1ZEl5SUNENjQ&authuser=0</a>)<br>
> >> >> > As described in the talk, we have a prototype implementation, and<br>
> >> >> > would like to start staging patches upstream. This RFC describes a<br>
> >> >> > breakdown of the major pieces. We would like to commit upstream<br>
> >> >> > gradually in several stages, with all functionality off by default.<br>
> >> >> > The core ThinLTO importing support and tuning will require frequent<br>
> >> >> > change and iteration during testing and tuning, and for that part<br>
> we<br>
> >> >> > would like to commit rapidly (off by default). See the proposed<br>
> >> >> > staged<br>
> >> >> > implementation described in the Implementation Plan section.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > ThinLTO Overview<br>
> >> >> > ==============<br>
> >> >> ><br>
> >> >> > See the talk slides linked above for more details. The following<br>
> is a<br>
> >> >> > high-level overview of the motivation.<br>
> >> >> ><br>
> >> >> > Cross Module Optimization (CMO) is an effective means for improving<br>
> >> >> > runtime performance, by extending the scope of optimizations across<br>
> >> >> > source module boundaries. Without CMO, the compiler is limited to<br>
> >> >> > optimizing within the scope of single source modules. Two solutions<br>
> >> >> > for enabling CMO are Link-Time Optimization (LTO), which is<br>
> currently<br>
> >> >> > supported in LLVM and GCC, and Lightweight-Interprocedural<br>
> >> >> > Optimization (LIPO). However, each of these solutions has<br>
> limitations<br>
> >> >> > that prevent it from being enabled by default. ThinLTO is a new<br>
> >> >> > approach that attempts to address these limitations, with a goal of<br>
> >> >> > being enabled more broadly. ThinLTO is designed with many of the<br>
> same<br>
> >> >> > principals as LIPO, and therefore its advantages, without any of<br>
> its<br>
> >> >> > inherent weakness. Unlike in LIPO where the module group decision<br>
> is<br>
> >> >> > made at profile training runtime, ThinLTO makes the decision at<br>
> >> >> > compile time, but in a lazy mode that facilitates large scale<br>
> >> >> > parallelism. The serial linker plugin phase is designed to be razor<br>
> >> >> > thin and blazingly fast. By default this step only does minimal<br>
> >> >> > preparation work to enable the parallel lazy importing performed<br>
> >> >> > later. ThinLTO aims to be scalable like a regular O2 build,<br>
> enabling<br>
> >> >> > CMO on machines without large memory configurations, while also<br>
> >> >> > integrating well with distributed build systems. Results from early<br>
> >> >> > prototyping on SPEC cpu2006 C++ benchmarks are in line with<br>
> >> >> > expectations that ThinLTO can scale like O2 while enabling much of<br>
> >> >> > the<br>
> >> >> > CMO performed during a full LTO build.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > A ThinLTO build is divided into 3 phases, which are referred to in<br>
> >> >> > the<br>
> >> >> > following implementation plan:<br>
> >> >> ><br>
> >> >> > phase-1: IR and Function Summary Generation (-c compile)<br>
> >> >> > phase-2: Thin Linker Plugin Layer (thin archive linker step)<br>
> >> >> > phase-3: Parallel Backend with Demand-Driven Importing<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > Implementation Plan<br>
> >> >> > ================<br>
> >> >> ><br>
> >> >> > This section gives a high-level breakdown of the ThinLTO support<br>
> that<br>
> >> >> > will be added, in roughly the order that the patches would be<br>
> staged.<br>
> >> >> > The patches are divided into three stages. The first stage<br>
> contains a<br>
> >> >> > minimal amount of preparation work that is not ThinLTO-specific.<br>
> The<br>
> >> >> > second stage contains most of the infrastructure for ThinLTO, which<br>
> >> >> > will be off by default. The third stage includes<br>
> >> >> > enhancements/improvements/tunings that can be performed after the<br>
> >> >> > main<br>
> >> >> > ThinLTO infrastructure is in.<br>
> >> >> ><br>
> >> >> > The second and third implementation stages will initially be very<br>
> >> >> > volatile, requiring a lot of iterations and tuning with large apps<br>
> to<br>
> >> >> > get stabilized. Therefore it will be important to do fast commits<br>
> for<br>
> >> >> > these implementation stages.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > 1. Stage 1: Preparation<br>
> >> >> > -------------------------------<br>
> >> >> ><br>
> >> >> > The first planned sets of patches are enablers for ThinLTO work:<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > a. LTO directory structure:<br>
> >> >> ><br>
> >> >> > Restructure the LTO directory to remove circular dependence when<br>
> >> >> > ThinLTO pass added. Because ThinLTO is being implemented as a SCC<br>
> >> >> > pass<br>
> >> >> > within Transforms/IPO, and leverages the LTOModule class for<br>
> linking<br>
> >> >> > in functions from modules, IPO then requires the LTO library. This<br>
> >> >> > creates a circular dependence between LTO and IPO. To break that,<br>
> we<br>
> >> >> > need to split the lib/LTO directory/library into lib/LTO/CodeGen<br>
> and<br>
> >> >> > lib/LTO/Module, containing LTOCodeGenerator and LTOModule,<br>
> >> >> > respectively. Only LTOCodeGenerator has a dependence on IPO,<br>
> removing<br>
> >> >> > the circular dependence.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > b. ELF wrapper generation support:<br>
> >> >> ><br>
> >> >> > Implement ELF wrapped bitcode writer. In order to more easily<br>
> >> >> > interact<br>
> >> >> > with tools such as $AR, $NM, and ?$LD -r? we plan to emit the<br>
> phase-1<br>
> >> >> > bitcode wrapped in ELF via the .llvmbc section, along with a symbol<br>
> >> >> > table. The goal is both to interact with these tools without<br>
> >> >> > requiring<br>
> >> >> > a plugin, and also to avoid doing partial LTO/ThinLTO across files<br>
> >> >> > linked with ?$LD -r? (i.e. the resulting object file should still<br>
> >> >> > contain ELF-wrapped bitcode to enable ThinLTO at the full link<br>
> step).<br>
> >> >> > I will send a separate design document for these changes, but the<br>
> >> >> > following is a high-level overview.<br>
> >> >> ><br>
> >> >> > Support was added to LLVM for reading ELF-wrapped bitcode<br>
> >> >> > (<a href="http://reviews.llvm.org/rL218078" target="_blank">http://reviews.llvm.org/rL218078</a>), but there does not yet exist<br>
> >> >> > support in LLVM/Clang for emitting bitcode wrapped in ELF. I plan<br>
> to<br>
> >> >> > add support for optionally generating bitcode in an ELF file<br>
> >> >> > containing a single .llvmbc section holding the bitcode.<br>
> >> >> > Specifically,<br>
> >> >> > the patch would add new options ?emit-llvm-bc-elf? (object file)<br>
> and<br>
> >> >> > corresponding ?emit-llvm-elf? (textual assembly code equivalent).<br>
> >> >> > Eventually these would be automatically triggered under ?-fthinlto<br>
> >> >> > -c?<br>
> >> >> > and ?-fthinlto -S?, respectively.<br>
> >> >> ><br>
> >> >> > Additionally, a symbol table will be generated in the ELF file,<br>
> >> >> > holding the function symbols within the bitcode. This facilitates<br>
> >> >> > handling archives of the ELF-wrapped bitcode created with $AR,<br>
> since<br>
> >> >> > the archive will have a symbol table as well. The archive symbol<br>
> >> >> > table<br>
> >> >> > enables gold to extract and pass to the plugin the constituent<br>
> >> >> > ELF-wrapped bitcode files. To support the concatenated llvmbc<br>
> section<br>
> >> >> > generated by ?$LD -r?, some handling needs to be added to gold and<br>
> to<br>
> >> >> > the backend driver to process each original module?s bitcode.<br>
> >> >> ><br>
> >> >> > The function index/summary will later be added as a special ELF<br>
> >> >> > section alongside the .llvmbc sections.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > 2. Stage 2: ThinLTO Infrastructure<br>
> >> >> > ----------------------------------------------<br>
> >> >> ><br>
> >> >> > The next set of patches adds the base implementation of the ThinLTO<br>
> >> >> > infrastructure, specifically those required to make ThinLTO<br>
> >> >> > functional<br>
> >> >> > and generate correct but not necessarily high-performing binaries.<br>
> It<br>
> >> >> > also does not include support to make debug support under -g<br>
> >> >> > efficient<br>
> >> >> > with ThinLTO.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > a. Clang/LLVM/gold linker options:<br>
> >> >> ><br>
> >> >> > An early set of clang/llvm patches is needed to provide options to<br>
> >> >> > enable ThinLTO (off by default), so that the rest of the<br>
> >> >> > implementation can be disabled by default as it is added.<br>
> >> >> > Specifically, clang options -fthinlto (used instead of -flto) will<br>
> >> >> > cause clang to invoke the phase-1 emission of LLVM bitcode and<br>
> >> >> > function summary/index on a compile step, and pass the appropriate<br>
> >> >> > option to the gold plugin on a link step. The -thinlto option will<br>
> be<br>
> >> >> > added to the gold plugin and llvm-lto tool to launch the phase-2<br>
> thin<br>
> >> >> > archive step. The -thinlto option will also be added to the ?opt?<br>
> >> >> > tool<br>
> >> >> > to invoke it as a phase-3 parallel backend instance.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > b. Thin-archive linking support in Gold plugin and llvm-lto:<br>
> >> >> ><br>
> >> >> > Under the new plugin option (see above), the plugin needs to<br>
> perform<br>
> >> >> > the phase-2 (thin archive) link which simply emits a combined<br>
> >> >> > function<br>
> >> >> > map from the linked modules, without actually performing the normal<br>
> >> >> > link. Corresponding support should be added to the standalone<br>
> >> >> > llvm-lto<br>
> >> >> > tool to enable testing/debugging without involving the linker and<br>
> >> >> > plugin.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > c. ThinLTO backend support:<br>
> >> >> ><br>
> >> >> > Support for invoking a phase-3 backend invocation (including<br>
> >> >> > importing) on a module should be added to the ?opt? tool under the<br>
> >> >> > new<br>
> >> >> > option. The main change under the option is to instantiate a Linker<br>
> >> >> > object used to manage the process of linking imported functions<br>
> into<br>
> >> >> > the module, efficient read of the combined function map, and enable<br>
> >> >> > the ThinLTO import pass.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > d. Function index/summary support:<br>
> >> >> ><br>
> >> >> > This includes infrastructure for writing and reading the function<br>
> >> >> > index/summary section. As noted earlier this will be encoded in a<br>
> >> >> > special ELF section within the module, alongside the .llvmbc<br>
> section<br>
> >> >> > containing the bitcode. The thin archive generated by phase-2 of<br>
> >> >> > ThinLTO simply contains all of the function index/summary sections<br>
> >> >> > across the linked modules, organized for efficient function lookup.<br>
> >> >> ><br>
> >> >> > Each function available for importing from the module contains an<br>
> >> >> > entry in the module?s function index/summary section and in the<br>
> >> >> > resulting combined function map. Each function entry contains that<br>
> >> >> > function?s offset within the bitcode file, used to efficiently<br>
> locate<br>
> >> >> > and quickly import just that function. The entry also contains<br>
> >> >> > summary<br>
> >> >> > information (e.g. basic information determined during parsing such<br>
> as<br>
> >> >> > the number of instructions in the function), that will be used to<br>
> >> >> > help<br>
> >> >> > guide later import decisions. Because the contents of this section<br>
> >> >> > will change frequently during ThinLTO tuning, it should also be<br>
> >> >> > marked<br>
> >> >> > with a version id for backwards compatibility or version checking.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > e. ThinLTO importing support:<br>
> >> >> ><br>
> >> >> > Support for the mechanics of importing functions from other<br>
> modules,<br>
> >> >> > which can go in gradually as a set of patches since it will be off<br>
> by<br>
> >> >> > default. Separate patches can include:<br>
> >> >> ><br>
> >> >> > - BitcodeReader changes to use function index to import/deserialize<br>
> >> >> > single function of interest (small changes, leverages existing lazy<br>
> >> >> > streamer support).<br>
> >> >> ><br>
> >> >> > - Minor LTOModule changes to pass the ThinLTO function to import<br>
> and<br>
> >> >> > its index into bitcode reader.<br>
> >> >> ><br>
> >> >> > - Marking of imported functions (for use in ThinLTO-specific symbol<br>
> >> >> > linking and global DCE, for example). This can be in-memory<br>
> >> >> > initially,<br>
> >> >> > but IR support may be required in order to support streaming<br>
> bitcode<br>
> >> >> > out and back in again after importing.<br>
> >> >> ><br>
> >> >> > - ModuleLinker changes to do ThinLTO-specific symbol linking and<br>
> >> >> > static promotion when necessary. The linkage type of imported<br>
> >> >> > functions changes to AvailableExternallyLinkage, for example.<br>
> Statics<br>
> >> >> > must be promoted in certain cases, and renamed in consistent ways.<br>
> >> >> ><br>
> >> >> > - GlobalDCE changes to support removing imported functions that<br>
> were<br>
> >> >> > not inlined (very small changes to existing pass logic).<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > f. ThinLTO Import Driver SCC pass:<br>
> >> >> ><br>
> >> >> > Adds Transforms/IPO/ThinLTO.cpp with framework for doing ThinLTO<br>
> via<br>
> >> >> > an SCC pass, enabled only under -fthinlto options. The pass<br>
> includes<br>
> >> >> > utilizing the thin archive (global function index/summary), import<br>
> >> >> > decision heuristics, invocation of LTOModule/ModuleLinker routines<br>
> >> >> > that perform the import, and any necessary callgraph updates and<br>
> >> >> > verification.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > g. Backend Driver:<br>
> >> >> ><br>
> >> >> > For a single node build, the gold plugin can simply write a<br>
> makefile<br>
> >> >> > and fork the parallel backend instances directly via parallel make.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > 3. Stage 3: ThinLTO Tuning and Enhancements<br>
> >> >> > ----------------------------------------------------------------<br>
> >> >> ><br>
> >> >> > This refers to the patches that are not required for ThinLTO to<br>
> work,<br>
> >> >> > but rather to improve compile time, memory, run-time performance<br>
> and<br>
> >> >> > usability.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > a. Lazy Debug Metadata Linking:<br>
> >> >> ><br>
> >> >> > The prototype implementation included lazy importing of<br>
> module-level<br>
> >> >> > metadata during the ThinLTO pass finalization (i.e. after all<br>
> >> >> > function<br>
> >> >> > importing is complete). This actually applies to all module-level<br>
> >> >> > metadata, not just debug, although it is the largest. This can be<br>
> >> >> > added as a separate set of patches. Changes to BitcodeReader,<br>
> >> >> > ValueMapper, ModuleLinker<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > b. Import Tuning:<br>
> >> >> ><br>
> >> >> > Tuning the import strategy will be an iterative process that will<br>
> >> >> > continue to be refined over time. It involves several different<br>
> types<br>
> >> >> > of changes: adding support for recording additional metrics in the<br>
> >> >> > function summary, such as profile data and optional heavier-weight<br>
> >> >> > IPA<br>
> >> >> > analyses, and tuning the import heuristics based on the summary and<br>
> >> >> > callsite context.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > c. Combined Function Map Pruning:<br>
> >> >> ><br>
> >> >> > The combined function map can be pruned of functions that are<br>
> >> >> > unlikely<br>
> >> >> > to benefit from being imported. For example, during the phase-2<br>
> thin<br>
> >> >> > archive plug step we can safely omit large and (with profile data)<br>
> >> >> > cold functions, which are unlikely to benefit from being inlined.<br>
> >> >> > Additionally, all but one copy of comdat functions can be<br>
> suppressed.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > d. Distributed Build System Integration:<br>
> >> >> ><br>
> >> >> > For a distributed build system, the gold plugin should write the<br>
> >> >> > parallel backend invocations into a makefile, including the mapping<br>
> >> >> > from the IR file to the real object file path, and exit. Additional<br>
> >> >> > work needs to be done in the distributed build system itself to<br>
> >> >> > distribute and dispatch the parallel backend jobs to the build<br>
> >> >> > cluster.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> > e. Dependence Tracking and Incremental Compiles:<br>
> >> >> ><br>
> >> >> > In order to support build systems that stage from local disks or<br>
> >> >> > network storage, the plugin will optionally support computation of<br>
> >> >> > dependent sets of IR files that each module may import from. This<br>
> can<br>
> >> >> > be computed from profile data, if it exists, or from the symbol<br>
> table<br>
> >> >> > and heuristics if not. These dependence sets also enable support<br>
> for<br>
> >> >> > incremental backend compiles.<br>
> >> >> ><br>
> >> >> ><br>
> >> >> ><br>
> >> >> > --<br>
> >> >> > Teresa Johnson | Software Engineer | <a href="mailto:tejohnson@google.com">tejohnson@google.com</a> |<br>
> >> >> > 408-460-2413<br>
> >> >> ><br>
> >> >> > _______________________________________________<br>
> >> >> > LLVM Developers mailing list<br>
> >> >> > <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
> >> >> > <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
> >> >><br>
> >> >> _______________________________________________<br>
> >> >> LLVM Developers mailing list<br>
> >> >> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
> >> >> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
> >> ><br>
> >> ><br>
> >><br>
> >><br>
> >><br>
> >> --<br>
> >> Teresa Johnson | Software Engineer | <a href="mailto:tejohnson@google.com">tejohnson@google.com</a> |<br>
> 408-460-2413<br>
> >><br>
> >> _______________________________________________<br>
> >> LLVM Developers mailing list<br>
> >> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
> >> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
><br>
><br>
><br>
> --<br>
> Teresa Johnson | Software Engineer | <a href="mailto:tejohnson@google.com">tejohnson@google.com</a> | 408-460-2413<br>
><br>
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</blockquote></div><br></div>