<div dir="ltr">That seems likely, however this particular issue had already been fixed in r236927.</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, May 12, 2015 at 1:56 AM, Hal Finkel <span dir="ltr"><<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">----- Original Message -----<br>
> From: "Steve King" <<a href="mailto:steve@metrokings.com">steve@metrokings.com</a>><br>
> To: <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br>
> Sent: Monday, May 11, 2015 11:40:56 PM<br>
> Subject: [LLVMdev] i1 types in MergeConsecutiveStores<br>
><br>
> Hello LLVM,<br>
><br>
> In DAGCombiner.cpp, MergeConsecutiveStores uses<br>
><br>
> int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;<br>
><br>
> <a href="https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L10669" target="_blank">https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L10669</a><br>
><br>
> which is broken for i1 types where getSizeInBits() == 1.  My<br>
> out-of-tree target hits this case and eventually LLVM asserts in<br>
> Type.cpp.<br>
><br>
> Is there some reason MergeConsecutiveStores should not expect to see<br>
> i1 types?<br>
<br>
</span>My impression is that there are a lot of things that are (still) broken for i1 memory operations (and i1 vectors). Patches welcome.<br>
<br>
 -Hal<br>
<span class="im HOEnZb"><br>
><br>
> Thanks,<br>
> -steve<br>
> _______________________________________________<br>
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><br>
<br>
</span><span class="HOEnZb"><font color="#888888">--<br>
Hal Finkel<br>
Assistant Computational Scientist<br>
Leadership Computing Facility<br>
Argonne National Laboratory<br>
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