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<pre>> beqz s4,1f<o:p></o:p></pre>
<pre>> li at,8704 ; **DELAY SLOT**<o:p></o:p></pre>
<pre>> j 2f<o:p></o:p></pre>
<pre>> udi VPU,vpu_find_first_neg_from_reduction_4_mcs05,1,zero ; **DELAY SLOT**<o:p></o:p></pre>
<pre>> 1:<o:p></o:p></pre>
<pre>> udi VPU,vpu_find_first_neg_from_reduction_4,1,zero<o:p></o:p></pre>
<pre>> 2:<o:p></o:p></pre>
<pre>> udi VPU,wait_req_pending,1,s1,0,0<o:p></o:p></pre>
<pre style="margin-bottom:12.0pt">><br>> Is there something I could try to exploit delay slots in branch instructions or are there any recent patch which deals with this?<o:p></o:p></pre>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">It looks like you're pulling instructions from the successor blocks into the delay slot. This is valid (with some exceptions like branches) and there is code in our backend
to do it. However, it's not enabled by default at the moment because it has some problems.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">The feature is guarded by -disable-mips-df-forward-search and -disable-mips-df-succbb-search (which both default to true) if you want to try it.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Also relevant: If you're on the trunk then you'll already have this Vasileios noticed an issue recently with KILL instructions preventing opportunities to fill the delay
slot. This was fixed in r235183 (<a href="http://reviews.llvm.org/rL235183">http://reviews.llvm.org/rL235183</a>).<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Ambuj Agrawal [mailto:ambujbwt@gmail.com]
<br>
<b>Sent:</b> 24 April 2015 17:14<br>
<b>To:</b> Daniel Sanders; llvmdev@cs.uiuc.edu<br>
<b>Subject:</b> MIPS - Filling delay slots<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<pre>Hi Daniel,<o:p></o:p></pre>
<pre style="margin-bottom:12.0pt">The Clang with LLVM backend seems to be missing some opportunities to fill branch delay slots for the MIPS M14K processor.<o:p></o:p></pre>
<pre>Example:<br>static inline void LOCAL(encode_position)(VARS)<o:p></o:p></pre>
<pre>{<o:p></o:p></pre>
<pre> if (vars->is_mcs05) {<o:p></o:p></pre>
<pre> udi(vpu_find_first_neg_from_reduction_4_mcs05, 1, 0);<o:p></o:p></pre>
<pre> } else {<o:p></o:p></pre>
<pre> udi(vpu_find_first_neg_from_reduction_4, 1, 0);<o:p></o:p></pre>
<pre> }<o:p></o:p></pre>
<pre>}<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>is giving<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>bfc03394: 12800004 beqz s4,bfc033a8 <rx4_eostf+0x4a4><o:p></o:p></pre>
<pre>bfc03398: 00000000 nop<o:p></o:p></pre>
<pre>bfc0339c: 70016450 udi VPU,vpu_find_first_neg_from_reduction_4_mcs05,1,zero<o:p></o:p></pre>
<pre>bfc033a0: 0bf00ceb j bfc033ac <rx4_eostf+0x4a8><o:p></o:p></pre>
<pre>bfc033a4: 00000000 nop<o:p></o:p></pre>
<pre>bfc033a8: 70016350 udi VPU,vpu_find_first_neg_from_reduction_4,1,zero<o:p></o:p></pre>
<pre>bfc033ac: 24012200 li at,8704<o:p></o:p></pre>
<pre>bfc033b0: 72201bd0 udi VPU,wait_req_pending,1,s1,0,0<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>I think the following is possible<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>beqz s4,1f<o:p></o:p></pre>
<pre>li at,8704 ; **DELAY SLOT**<o:p></o:p></pre>
<pre>j 2f<o:p></o:p></pre>
<pre>udi VPU,vpu_find_first_neg_from_reduction_4_mcs05,1,zero ; **DELAY SLOT**<o:p></o:p></pre>
<pre>1:<o:p></o:p></pre>
<pre>udi VPU,vpu_find_first_neg_from_reduction_4,1,zero<o:p></o:p></pre>
<pre>2:<o:p></o:p></pre>
<pre>udi VPU,wait_req_pending,1,s1,0,0<o:p></o:p></pre>
<pre style="margin-bottom:12.0pt"><br>Is there something I could try to exploit delay slots in branch instructions or are there any recent patch which deals with this?<o:p></o:p></pre>
<pre>Thanks,<o:p></o:p></pre>
<pre>Ambuj<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
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