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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>An assembler frontend for converting to MCInsts is a possibility. The parser for that would probably be generated using a third party parser generator. At that point we could just substitute use of the TableGen match tables for the generated library. Do you know if anyone’s considered including a parser lib like this before?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>The TableGen changes I alluded to would get us close to parsing without hacks though it would still be deficient compared to a full parser. These changes would probably be the least amount of deviation from other targets depending on what everyone wants long-term.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'> Reid Kleckner [mailto:rnk@google.com] <br><b>Sent:</b> Tuesday, April 14, 2015 1:17 PM<br><b>To:</b> Colin LeMahieu<br><b>Cc:</b> LLVM Developers Mailing List<br><b>Subject:</b> Re: [LLVMdev] RFC building a target MCAsmParser<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>Frankly, the MC assembler infrastructure is pretty weak. I've spoken personally to some of the developers who wrote it, and they said they know it's bad and suggested that it be rewritten. My experience from attempting to make MC parse Intel x86 asm confirms this.<o:p></o:p></p><div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Here's some questions for you:<o:p></o:p></p></div><div><p class=MsoNormal>Do you need a high-level macro assembler designed for human consumption?<br>Do you need Clang to understand inline assembly that uses these high-level assembly constructs?<o:p></o:p></p></div><div><p class=MsoNormal>Do you need the assembler to parse the output of `clang -S`?<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>It might be best to have your own small frontend for the macro assembler language that produces MCInsts which can be printed using a more traditional gas-like mneumonic. Running llvm-mc on a hexagon assembly file and re-emitting assembly would parse the high-level assembly and produce the low-level assembly.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Alternatively, you can do as you say and try to make MC into more of a real language frontend. The major problem is that lexing rules are not the same across all targets, even when they all use a gas-like syntax.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>On Tue, Apr 14, 2015 at 10:58 AM, Colin LeMahieu <<a href="mailto:colinl@codeaurora.org" target="_blank">colinl@codeaurora.org</a>> wrote:<o:p></o:p></p><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Hi everyone. We’re interested in contributing a Hexagon assembler to MC and we’re looking for comments on a good way to integrate the grammar in to the infrastructure.<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>We rely on having a robust assembler because we have a large base of developers that write in assembly due to low power requirements for mobile devices. We put in some C-like concepts to make the syntax easier and this design is fairly well received by users.<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>The following is a list of grammar snippets we’ve had trouble integrating in to the asm parser framework.<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Instruction packets are optionally enclosed in braces.<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> { r0 = add(r1, r2) r1 = add(r2, r0) }<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Register can be the beginning of a statement. Register transfers have no mnemonic.<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> r0 = r1<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Double registers have a colon in the middle which can look like a label<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> r1:0 = add(r3:2, r5:4)<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Predicated variants for many instructions<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> if(p1) r0 = add(r1, r2)<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Dense semantics for DSP applications. Complex multiply optionally shifting result left by 1 with optional rounding and optional saturation<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> r0 = cmpy(r1, r2):<<1:rnd:sat<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Hardware loops ended by optional packet suffix<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> { r0 = r1 }:endloop0:endloop1<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>We found the Hexagon grammar to be straight forward to implement using plain lex / parse but harder within the MCTargetAsmParser. <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>We were thinking a way to get the grammar to work would involve modifying tablegen and the main asm parser loop. We’d have to make tablegen break down each instructions in to a sequence of tokens and build a sorted matching table based on the set of these sequences. The matching loop would bisect this sorted list looking for a match. We think existing grammars would be unaffected; all existing instructions start with a mnemonic so their first token would be an identifier followed by the same sequence of tokens they currently have.<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Let us know if we’re likely to run in to any issues making these changes or if there are other recommendations on what we could do. Thanks!<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>Qualcomm Innovation Center, Inc.</span><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><br></span><span style='color:black'>The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, </span><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><br></span><span style='color:black'>a Linux Foundation Collaborative Project</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p></div></div><p class=MsoNormal style='margin-bottom:12.0pt'><br>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><o:p></o:p></p></blockquote></div><p class=MsoNormal><o:p> </o:p></p></div></div></div></div></body></html>