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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">Your clang invocation below works for me, and generates target triple in the llvm IR of<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">i386.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">And then in the specific options for the functions it generates the following:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">; Function Attrs: nounwind<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">define float @foo() #0 {<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">entry:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"> ret float 1.000000e+00<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">}<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"=<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">"true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-ma<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">th"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-fe<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">atures"="+mmx,-sse" "unsafe-fp-math"="false" "use-soft-float"="false" }<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">The attributes indicate to allow mmx, disallow sse, so this certainly looks like it might work. I don’t<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">know whether work has been done to specifically do something special for this combination, since<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">use of MMX overlaps with X87 floating point state. The processors that support mmx, but not SSE<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">would be<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">Pentium w MMX processor<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">Pentium II family processors<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">Kevin<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> suyog sarda [mailto:sardask01@gmail.com]
<br>
<b>Sent:</b> Friday, April 10, 2015 2:51 AM<br>
<b>To:</b> Smith, Kevin B<br>
<b>Cc:</b> Sanjay Patel; David Majnemer; LLVM Developers Mailing List<br>
<b>Subject:</b> Re: [LLVMdev] MMX/SSE subtarget feature in IR<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hi Kevin,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">I had another query for 32 bit x86. (Apology for being naive) <o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">I guess <span style="color:black">the default CPU on 32-bit x86 is 'pentium4', which has SSE as seen in getX86TargetCPU() in tools/clang/lib/Driver/Tools.cpp:</span><o:p></o:p></p>
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<pre style="white-space:pre-wrap"><span style="color:black">static const char *getX86TargetCPU(const ArgList &Args,<o:p></o:p></span></pre>
<pre><span style="color:black"> const llvm::Triple &Triple) {<o:p></o:p></span></pre>
<pre><span style="color:black">...<o:p></o:p></span></pre>
<pre><span style="color:black"> // Everything else goes to x86-64 in 64-bit mode.<o:p></o:p></span></pre>
<pre><span style="color:black"> if (Is64Bit)<o:p></o:p></span></pre>
<pre><span style="color:black"> return "x86-64";<o:p></o:p></span></pre>
<pre><span style="color:black"><o:p> </o:p></span></pre>
<pre><span style="color:black"> switch (Triple.getOS()) {<o:p></o:p></span></pre>
<pre><span style="color:black"> case llvm::Triple::FreeBSD:<o:p></o:p></span></pre>
<pre><span style="color:black"> case llvm::Triple::NetBSD:<o:p></o:p></span></pre>
<pre><span style="color:black"> case llvm::Triple::OpenBSD:<o:p></o:p></span></pre>
<pre><span style="color:black"> return "i486";<o:p></o:p></span></pre>
<pre><span style="color:black"> case llvm::Triple::Haiku:<o:p></o:p></span></pre>
<pre><span style="color:black"> return "i586";<o:p></o:p></span></pre>
<pre><span style="color:black"> case llvm::Triple::Bitrig:<o:p></o:p></span></pre>
<pre><span style="color:black"> return "i686";<o:p></o:p></span></pre>
<pre><span style="color:black"> default:<o:p></o:p></span></pre>
<pre><span style="color:black"> // Fallback to p4.<o:p></o:p></span></pre>
<pre><span style="color:black"> return "pentium4";<o:p></o:p></span></pre>
<pre><span style="color:black"> }<o:p></o:p></span></pre>
<pre><span style="color:black">}<o:p></o:p></span></pre>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="color:black">Is there any 32-bit CPU with MMX feature but without SSE feature?</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="color:black">Can it be done as follows :</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="color:black">$ clang 1.c -mmmx -mno-sse -emit-llvm -S -target i386.</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="color:black">My intention is to generate IR for x86 32 bit CPU with MMX feature but without SSE feature and further investigate if vectorization triggers for 32 bit architecture with MMX feature only.</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Regards,<o:p></o:p></p>
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<p class="MsoNormal">Suyog Sarda<o:p></o:p></p>
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