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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Better. With this test I see:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">% clang -S -O3 -Rpass=loop-vectorize test.c<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">test.c:3:3: remark: vectorized loop (vectorization factor: 4, unrolling<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> interleave factor: 2) [-Rpass=loop-vectorize]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> for(i = 0; i < 1000; i++) {<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> ^<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">% clang -S -O3 -o test1.s –mcpu=cortex-a57 -Rpass=loop-vectorize test.c<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">test.c:3:3: remark: vectorized loop (vectorization factor: 4, unrolling<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> interleave factor: 4) [-Rpass=loop-vectorize]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> for(i = 0; i < 1000; i++) {<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> ^<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Both use SIMD instructions.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Changing the code to use a variable for the loop limit works OK as well as changing int to float.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">So I guess it is the return in dot.c that is causing a problem.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I will file a bug since I think the vectorizer should handle that case.<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Michael Zolotukhin [mailto:mzolotukhin@apple.com]
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<b>Sent:</b> Monday, February 09, 2015 3:53 PM<br>
<b>To:</b> Ralph Campbell<br>
<b>Cc:</b> Arnaud A. de Grandmaison; llvmdev@cs.uiuc.edu<br>
<b>Subject:</b> Re: [LLVMdev] aarch64 status for generating SIMD instructions<o:p></o:p></span></p>
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<p class="MsoNormal">From this message it looks like the vectorizer is having some general problems with the testcase. I’d suggest to try the simplest case for the beginning, just to make sure vectorizer works. Like this:<o:p></o:p></p>
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<p class="MsoNormal"> a[i] = b[i] + c[i];<o:p></o:p></p>
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<p class="MsoNormal"> }<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">If you compile it with ‘clang -O3 -arch arm64 -S’, you should see the SIMD instructions. If you do see them, it means that your original test is too complicated for the vectorizer right now (that might be due to some bug) - feel free to
file a bug.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks,<o:p></o:p></p>
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<p class="MsoNormal">Michael<o:p></o:p></p>
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<p class="MsoNormal">On Feb 9, 2015, at 3:33 PM, Ralph Campbell <<a href="mailto:ralph.campbell@broadcom.com">ralph.campbell@broadcom.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">% clang -S -O3 -mcpu=cortex-a57 -ffast-math -Rpass-analysis=loop-vectorize dot.c</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">dot.c:15:1: remark: loop not vectorized: value that could not be identified as</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> reduction is used outside the loop [-Rpass-analysis=loop-vectorize]</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">dot.c:15:1: note: could not determine the original source location for :0:0</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I found “llvm-as < /dev/null | llc -march=aarch64 -mattr=help” which listed a bunch of features but when I tried</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">adding “-mfpu=neon” or “-mattr=+neon”, clang complained that the option was unrecognized.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span class="apple-converted-space"><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> </span></span><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">Michael
Zolotukhin [<a href="mailto:mzolotukhin@apple.com"><span style="color:purple">mailto:mzolotukhin@apple.com</span></a>]<span class="apple-converted-space"> </span><br>
<b>Sent:</b><span class="apple-converted-space"> </span>Monday, February 09, 2015 3:08 PM<br>
<b>To:</b><span class="apple-converted-space"> </span>Ralph Campbell<br>
<b>Cc:</b><span class="apple-converted-space"> </span>Arnaud A. de Grandmaison;<span class="apple-converted-space"> </span><a href="mailto:llvmdev@cs.uiuc.edu"><span style="color:purple">llvmdev@cs.uiuc.edu</span></a><br>
<b>Subject:</b><span class="apple-converted-space"> </span>Re: [LLVMdev] aarch64 status for generating SIMD instructions</span><o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Hi Ralph,<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">A bunch of useful options for vectorizers is listed in [1].<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Also, what you see might be a target-independent issue, not an aarch64-specific. If you can share the code you tested I can try to explain why vectorizer fails to handle it, and hopefully we can fix it later:)<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Thanks,<o:p></o:p></p>
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<p class="MsoNormal">Michael<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">[1] <a href="http://llvm.org/docs/Vectorizers.html"><span style="color:purple">http://llvm.org/docs/Vectorizers.html</span></a><o:p></o:p></p>
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<p class="MsoNormal">On Feb 9, 2015, at 2:19 PM, Ralph Campbell <<a href="mailto:ralph.campbell@broadcom.com"><span style="color:purple">ralph.campbell@broadcom.com</span></a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">So far, all I have tried is –O3 and with & without “-mcpu=cortex-a57”.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I’m new to LLVM so I’m not familiar with what optimization flags are available.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I tried poking around in the LLVM documentation but haven’t found a definitive list.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">The clang man page is skimpy on details.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span class="apple-converted-space"><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> </span></span><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">Arnaud
A. de Grandmaison [<a href="mailto:arnaud.degrandmaison@arm.com"><span style="color:purple">mailto:arnaud.degrandmaison@arm.com</span></a>]<span class="apple-converted-space"> </span><br>
<b>Sent:</b><span class="apple-converted-space"> </span>Monday, February 09, 2015 2:11 PM<br>
<b>To:</b><span class="apple-converted-space"> </span>Ralph Campbell<br>
<b>Cc:</b><span class="apple-converted-space"> </span><a href="mailto:llvmdev@cs.uiuc.edu"><span style="color:purple">llvmdev@cs.uiuc.edu</span></a><br>
<b>Subject:</b><span class="apple-converted-space"> </span>RE: aarch64 status for generating SIMD instructions</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span lang="EN-GB" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Which compiler flags have you been using ?</span><o:p></o:p></p>
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<p class="MsoNormal"><span lang="EN-GB" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span lang="EN-GB" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">There is definitely support for AArch64’s SIMD instructions, but their use depends on what the vectorizers can do with your code.</span><o:p></o:p></p>
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<p class="MsoNormal"><span lang="EN-GB" style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span class="apple-converted-space"><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> </span></span><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""><a href="mailto:llvmdev-bounces@cs.uiuc.edu"><span style="color:purple">llvmdev-bounces@cs.uiuc.edu</span></a><span class="apple-converted-space"> </span>[<a href="mailto:llvmdev-bounces@cs.uiuc.edu"><span style="color:purple">mailto:llvmdev-bounces@cs.uiuc.edu</span></a>]<span class="apple-converted-space"> </span><b>On
Behalf Of<span class="apple-converted-space"> </span></b>Ralph Campbell<br>
<b>Sent:</b><span class="apple-converted-space"> </span>09 February 2015 22:30<br>
<b>To:</b><span class="apple-converted-space"> </span><a href="mailto:llvmdev@cs.uiuc.edu"><span style="color:purple">llvmdev@cs.uiuc.edu</span></a><br>
<b>Subject:</b><span class="apple-converted-space"> </span>[LLVMdev] aarch64 status for generating SIMD instructions</span><o:p></o:p></p>
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<p class="MsoNormal"><span lang="EN-GB" style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">I’m using Fedora 22 and gcc 4.9.2 to run llvm 3.5.1 on an ARM Juno reference box (cortex A53 & A57).</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">I tried compiling some simple functions like dot product and axpy() into assembly to see if any of the SIMD instructions were generated (they weren’t).</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Perhaps I’m missing some compiler flag to enable it.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Does anyone know what the status is for aarch64 generating SIMD instructions?</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Anyone coordinating or leading this effort? (if there is one)</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">_______________________________________________<br>
LLVM Developers mailing list<br>
<a href="mailto:LLVMdev@cs.uiuc.edu"><span style="color:purple">LLVMdev@cs.uiuc.edu</span></a><span class="apple-converted-space"> </span> <a href="http://llvm.cs.uiuc.edu/"><span style="color:purple">http://llvm.cs.uiuc.edu</span></a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev"><span style="color:purple">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</span></a></span><o:p></o:p></p>
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