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</o:shapelayout></xml><![endif]--></head><body lang=EN-GB link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='color:#1F497D'>You can try something along the lines of “-03 -</span><span style='color:#1F497D'> <span lang=EN-US>mcpu=cortex-a57 –mfpu=neon –ffast-math”</span></span><span style='color:#1F497D'><o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0cm 0cm 0cm 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Ralph Campbell [mailto:ralph.campbell@broadcom.com] <br><b>Sent:</b> 09 February 2015 23:20<br><b>To:</b> Arnaud De Grandmaison<br><b>Cc:</b> llvmdev@cs.uiuc.edu<br><b>Subject:</b> RE: aarch64 status for generating SIMD instructions<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><span lang=EN-US style='color:#1F497D'>So far, all I have tried is –O3 and with & without “-mcpu=cortex-a57”.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='color:#1F497D'>I’m new to LLVM so I’m not familiar with what optimization flags are available.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='color:#1F497D'>I tried poking around in the LLVM documentation but haven’t found a definitive list.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='color:#1F497D'>The clang man page is skimpy on details.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Arnaud A. de Grandmaison [<a href="mailto:arnaud.degrandmaison@arm.com">mailto:arnaud.degrandmaison@arm.com</a>] <br><b>Sent:</b> Monday, February 09, 2015 2:11 PM<br><b>To:</b> Ralph Campbell<br><b>Cc:</b> <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br><b>Subject:</b> RE: aarch64 status for generating SIMD instructions<o:p></o:p></span></p></div></div><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>Which compiler flags have you been using ?<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>There is definitely support for AArch64’s SIMD instructions, but their use depends on what the vectorizers can do with your code.<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0cm 0cm 0cm 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> <a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a> [<a href="mailto:llvmdev-bounces@cs.uiuc.edu">mailto:llvmdev-bounces@cs.uiuc.edu</a>] <b>On Behalf Of </b>Ralph Campbell<br><b>Sent:</b> 09 February 2015 22:30<br><b>To:</b> <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br><b>Subject:</b> [LLVMdev] aarch64 status for generating SIMD instructions<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><span lang=EN-US>I’m using Fedora 22 and gcc 4.9.2 to run llvm 3.5.1 on an ARM Juno reference box (cortex A53 & A57).<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>I tried compiling some simple functions like dot product and axpy() into assembly to see if any of the SIMD instructions were generated (they weren’t).<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Perhaps I’m missing some compiler flag to enable it.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>Does anyone know what the status is for aarch64 generating SIMD instructions?<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Anyone coordinating or leading this effort? (if there is one)<o:p></o:p></span></p></div></div></div></body></html>