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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">This is memop definition:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> return Subtarget->hasVectorUAMem()<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> || cast<LoadSDNode>(N)->getAlignment() >= 16;<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">}]>;<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I want to fold all unaligned loads in instructions on AVX architectures.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I’ll write some tests for this.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo1">
<![if !supportLists]><span style="font-family:"Calibri","sans-serif";color:#31849B"><span style="mso-list:Ignore">-<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]><span dir="LTR"></span><b><i><span style="color:#31849B"> Elena<o:p></o:p></span></i></b></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Das, Dibyendu [mailto:Dibyendu.Das@amd.com]
<br>
<b>Sent:</b> Monday, December 15, 2014 14:12<br>
<b>To:</b> Demikhovsky, Elena; Chandler Carruth<br>
<b>Cc:</b> llvmdev@cs.uiuc.edu<br>
<b>Subject:</b> RE: [LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Are there some test cases or micro bms u r planning to use ?<br>
<br>
Sent from my Windows Phone<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">From:
</span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><a href="mailto:elena.demikhovsky@intel.com">Demikhovsky, Elena</a></span><br>
<b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Sent: </span>
</b><span lang="AR-SA" style="font-size:11.0pt;font-family:"Calibri","sans-serif"">ý</span><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">12/<span lang="AR-SA">ý</span>15/<span lang="AR-SA">ý</span>2014 5:16 PM</span><br>
<b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">To: </span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><a href="mailto:Dibyendu.Das@amd.com">Das, Dibyendu</a>;
<a href="mailto:chandlerc@gmail.com">Chandler Carruth</a></span><br>
<b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Cc: </span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a></span><br>
<b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Subject: </span>
</b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">RE: [LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Ok, if no objections, I’ll add “HasVectorUAMem” feature to all AVX processors.</span><o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I’ll allow to fold an unaligned load to instruction.</span><o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal" style="margin-left:36.0pt;text-indent:-18.0pt"><span style="font-family:"Calibri","sans-serif";color:#31849B">-</span><span style="font-size:7.0pt;color:#31849B">
</span><b><i><span style="color:#31849B"> Elena</span></i></b><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Das, Dibyendu [<a href="mailto:Dibyendu.Das@amd.com">mailto:Dibyendu.Das@amd.com</a>]
<br>
<b>Sent:</b> Monday, December 15, 2014 07:01<br>
<b>To:</b> Chandler Carruth; Demikhovsky, Elena<br>
<b>Cc:</b> <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br>
<b>Subject:</b> RE: [LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets</span><o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">AFAIK, there is no additional penalty for AMD processors.</span><o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">
<a href="mailto:llvmdev-bounces@cs.uiuc.edu">llvmdev-bounces@cs.uiuc.edu</a> [<a href="mailto:llvmdev-bounces@cs.uiuc.edu">mailto:llvmdev-bounces@cs.uiuc.edu</a>]
<b>On Behalf Of </b>Chandler Carruth<br>
<b>Sent:</b> Monday, December 15, 2014 3:57 AM<br>
<b>To:</b> Demikhovsky, Elena<br>
<b>Cc:</b> <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br>
<b>Subject:</b> Re: [LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets</span><o:p></o:p></p>
<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">FWIW, this makes sense to me. I'd be interested to hear from folks that are supporting AMD processors which do support AVX to ensure that there isn't an undue runtime penalty for these.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">On Sun, Dec 14, 2014 at 7:08 AM, Demikhovsky, Elena <<a href="mailto:elena.demikhovsky@intel.com" target="_blank">elena.demikhovsky@intel.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Hi,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">I think that
</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> "HasVectorUAMem", "true",</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> "Allow unaligned memory operands on vector/SIMD instructions">;</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">should be switched-ON on AVX and AVX-512 instructions because:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">According to the AVX spec:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">“</span><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">Most arithmetic and data processing instructions encoded using the VEX prefix and</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">performing memory accesses have more flexible memory alignment requirements</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">than instructions that are encoded without the VEX prefix. Specifically,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:14.0pt">• </span><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">With the exception of explicitly aligned 16 or 32 byte SIMD load/store instructions,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">most VEX-encoded, arithmetic and data processing instructions operate in</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">a flexible environment regarding memory address alignment, i.e. VEX-encoded</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">instruction with 32-byte or 16-byte load semantics will support unaligned load</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">operation by default. Memory arguments for most instructions with VEX prefix</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">operate normally without causing #GP(0) on any byte-granularity alignment</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">(unlike Legacy SSE instructions).”</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">And the same for AVX-512.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Verdana","sans-serif"">We do not require any alignment while folding loads on the “Peephole Optimizations” on these targets.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal" style="text-indent:-18.0pt"><span style="font-size:10.0pt;font-family:Symbol;color:#31849B">·</span><span style="font-size:7.0pt;color:#31849B">
</span><b><i><span style="color:#31849B">Elena</span></i></b><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""> </span><o:p></o:p></p>
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