<div dir="ltr">Hi Nick,<div><br></div><div>Thanks for providing this info. I was looking for the patch which caused this behaviour in 3.5 not occuring in 3.4.2. Thanks for directing me to the patches.</div><div><br></div><div>Regards,</div><div>Mayur</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Nov 26, 2014 at 2:11 AM, Nick Lewycky <span dir="ltr"><<a href="mailto:nicholas@mxc.ca" target="_blank">nicholas@mxc.ca</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">Mayur Pandey wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi Tim,<br>
<br>
Thanks for the response. Even I thought this might be the result of tail<br>
call optimisation in O1, but with clang-3.4.2 this behaviour is not seen<br>
in O1, so wanted to know which change triggered this behaviour in O1 in<br>
clang-3.5.<br>
</blockquote>
<br></span>
Between clang 3.4 and clang 3.5, I rewrote tail call deduction in the optimizer:<br>
<br>
<a href="http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140505/215891.html" target="_blank">http://lists.cs.uiuc.edu/<u></u>pipermail/llvm-commits/Week-<u></u>of-Mon-20140505/215891.html</a><br>
and also made a matching change to clang NRVO which causes us to LLVM IR that use the above optimization more often:<br>
<br>
<a href="http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20140428/104594.html" target="_blank">http://lists.cs.uiuc.edu/<u></u>pipermail/cfe-commits/Week-of-<u></u>Mon-20140428/104594.html</a><br>
<br>
That might be it.<br>
<br>
Nick<br>
<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">
On Mon, Nov 24, 2014 at 10:55 PM, Tim Northover <<a href="mailto:tnorthover@apple.com" target="_blank">tnorthover@apple.com</a><br></span><span class="">
<mailto:<a href="mailto:tnorthover@apple.com" target="_blank">tnorthover@apple.com</a>>> wrote:<br>
<br>
Hi Mayur,<br>
<br>
> On 24 Nov 2014, at 07:00, MAYUR PANDEY <<a href="mailto:mayur.p@samsung.com" target="_blank">mayur.p@samsung.com</a><br></span><span class="">
<mailto:<a href="mailto:mayur.p@samsung.com" target="_blank">mayur.p@samsung.com</a>>> wrote:<br>
> In the assembly generated with O0, we are getting the "blx"<br>
instruction whereas with O1 we get "bx" (in 3.4.2 we used to get<br>
"blx" for both O0 and O1).<br>
><br>
> Is this because of this patch: [llvm] r214959 - ARM: do not<br>
generate BLX instructions on Cortex-M CPUs<br>
<br>
Isn't this just the usual tail call optimisations kicking in at O1?<br>
Or is there some problem with this behaviour that I'm missing (both<br>
variants seem to be supported on v5t).<br>
<br>
Cheers.<br>
<br>
Tim.<br>
<br>
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<br>
<br>
<br>
<br>
--<br>
Thanx & Regards<br></span>
*Mayur Pandey *<span class=""><br>
Lead Engineer<br>
Samsung R&D Institute India<br>
Bangalore<br>
+91-9742959541<br>
<br>
<br>
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<br>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature"><div dir="ltr"><div>Thanx & Regards <br></div>
<div><b>Mayur Pandey </b><br></div>
<div style="color:rgb(0,0,0)">Lead Engineer<br></div><div>Samsung R&D Institute India<br>Bangalore<br>+91-9742959541<br><font color="#3333ff"></font><font color="#3333ff"> <br></font></div>
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