<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><div>On Oct 24, 2014, at 4:24 AM, Demikhovsky, Elena <<a href="mailto:elena.demikhovsky@intel.com">elena.demikhovsky@intel.com</a>> wrote:</div><div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="font-family: Helvetica; font-size: 14px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><font face="Calibri" size="2"><span style="font-size: 11pt;"><div><font color="#1F497D">Hi,</font></div><div><font color="#1F497D"> </font></div><div><font color="#1F497D">We would like to add support for masked vector loads and stores by introducing new target-independent intrinsics. The loop vectorizer will then be enhanced to optimize loops containing conditional memory accesses by generating these intrinsics for existing targets such as AVX2 and AVX-512. The vectorizer will first ask the target about availability of masked vector loads and stores. The SLP vectorizer can potentially be enhanced to use these intrinsics as well.</font></div><div><font color="#1F497D"> </font></div><div><font color="#1F497D">The intrinsics would be legal for all targets; targets that do not support masked vector loads or stores will scalarize them.</font></div></span></font></div></blockquote><div><br></div><div>I do agree that we would like to have one IR node to capture these so that they survive until ISel and that their specific semantics can be expressed. However, can you discuss the other options (new IR instructions, target-specific intrinsics) and why you went with target-independent intrinsics.</div><div><br></div><div>My intuition would have been to go with target-specific intrinsics until we have something solid implemented and then potentially turn this into native IR instructions as the next step (for other targets, etc.). I am particularly worried whether we really want to generate these for targets that don’t have vector predication support.</div><div><br></div><div><div>There is also the related question of vector predicating any other instruction beyond just loads and stores which AVX512 supports. This is probably a smaller gain but should probably be part of the plan as well.</div><div><br></div></div><div>Adam</div><br><blockquote type="cite"><div style="font-family: Helvetica; font-size: 14px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><font face="Calibri" size="2"><span style="font-size: 11pt;"><div><font color="#1F497D">The addressed memory will not be touched for masked-off lanes. In particular, if all lanes are masked off no address will be accessed.</font></div><div><font color="#1F497D"> </font></div><div><font color="#1F497D"> call void @llvm.masked.store (i32* %addr, <16 x i32> %data, i32 4, <16 x i1> %mask)</font></div><div><font color="#1F497D"> </font></div><div><font color="#1F497D"> %data = call <8 x i32> @llvm.masked.load (i32* %addr, <8 x i32> %passthru, i32 4, <8 x i1> %mask)</font></div><div><font color="#1F497D"> </font></div><div><font color="#1F497D">where %passthru is used to fill the elements of %data that are masked-off (if any; can be zeroinitializer or undef).</font></div><div><font color="#1F497D"> </font></div><div><font color="#1F497D">Comments so far, before we dive into more details?</font></div><div><font color="#1F497D"> </font></div><div><font color="#1F497D">Thank you.</font></div><div><font color="#1F497D"> </font></div><div><font color="#1F497D">- Elena and Ayal</font></div><div><font color="#1F497D"> </font></div><div> </div></span></font><p>---------------------------------------------------------------------<br>Intel Israel (74) Limited</p><p>This e-mail and any attachments may contain confidential material for<br>the sole use of the intended recipient(s). Any review or distribution<br>by others is strictly prohibited. If you are not the intended<br>recipient, please contact the sender and delete all copies.</p></div></blockquote></div><br></body></html>