<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On Jul 31, 2014, at 7:23 PM, Tom Stellard <<a href="mailto:tom@stellard.net">tom@stellard.net</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">On Thu, Jul 31, 2014 at 06:41:06PM -0400, kewuzhang wrote:<br><blockquote type="cite">Hi All,<span class="Apple-converted-space"> </span><br><br>Is it possible to initialize(set up) register attributes when we define an instruction?<br><br>like <br><br>if a register is defined like this:<br><br>" class SC_Register<bits<8> register_num,<span class="Apple-converted-space"> </span><br> <span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-converted-space"> </span>REG_FLAG SC_X,<br><span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-converted-space"> </span>REG_FLAG SC_Y,<br><span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-converted-space"> </span>REG_FLAG SC_Z,<br><span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-converted-space"> </span>REG_FLAG SC_W,<br> <span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-converted-space"> </span>string asmstr> : Register<asmstr><br>{<br><span class="Apple-tab-span" style="white-space: pre;"> </span><br> <span class="Apple-tab-span" style="white-space: pre;"> </span>let HWEncoding{7-0} = register_num; // register_num<br><span class="Apple-tab-span" style="white-space: pre;"> </span>let HWEncoding{8} = SC_X; <br><span class="Apple-tab-span" style="white-space: pre;"> </span>let HWEncoding{9} = SC_Y; <br>…..<br>}”<br><br>can I set up the input/ouput register flags like this? or some other way in codegen to make the register flags are set up based on the instructions?<br><br>let Constraints = “$dst.SC_X =1, $src.SC_Y =0" in<span class="Apple-converted-space"> </span><br></blockquote><br>This isn't what Constraints are for. Constraints can be either tied<br>operands e.g. $dst = $src or @earlyclober $dst, meaning that the $dst<br>may be written before all source registers are read.<br><br>Can you explain more about what you are trying to do? It looks like you<br>might be trying to force an instruction to uses a specific component of<br>a vector register.<br><br></div></blockquote><div><br></div>Yes, that is pretty much what i want to do. If I can initialize it in the instruction definition stage( it is operation related).</div><div>Then I can directly access it for the machine instruction emit.</div><div>That would be nice.</div><div><br></div><div>Tks</div><div><br></div><div>kevin</div><div><br><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">This is something that the R600 backend does a lot. Take a look at<br>lib/Target/R600/ R600RegisterInfo.td and R600Instructions.td<br><br>-Tom<br><br><blockquote type="cite">{<br> def GENri : my_instr <op, 0, (outs GPR_V4_R32:$dst), (ins GPR_V4_R32:$src),<br> !strconcat(asmstr, " $dst, ""$src"),<span class="Apple-converted-space"> </span><br> [(set v4i32:$dst, (node v4i32:$src)]>;<br><br>}<br><br><br><br>tks<br><br><br>kevin<br></blockquote><br><blockquote type="cite">_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a><span class="Apple-converted-space"> </span> <a href="http://llvm.cs.uiuc.edu/">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a></blockquote></div></blockquote></div><br></body></html>