<div dir="ltr">Hi Tom,<div><br></div><div>Thanks for getting back to me. Let me elaborate on my problem a bit.</div><div><br></div><div>Currently, Selection DAG generates the following for stack load / store when needed:</div>
<div><br></div><div>LOAD <FrameIndex #0>, 0, .... ; 0 = offset</div><div><br></div><div>I would like to change the above to:</div><div><br></div><div>LOAD <FrameIndex #0>, %Dummy_GPR, 0, ....</div><div><br></div>
<div>The Dummy_GPR is used for 32-bit pointers, which will be ignored by later passes. The idea is to have a single instruction format for both 32-bit and 64-bit load / store.</div><div><br></div><div>I have already modifed TD to reflect instruction format changes. </div>
<div><br></div><div>I am currently hitting an assertion in InstrEmitter::EmitMachineNode due to mismatch between TD definition and SDNode definition.</div><div><br></div><div>I'm not quite sure how to go about changing SDNode definition for LOAD to reflect TD changes.<br>
</div><div><br></div><div>Any suggestions are much appreciated.</div><div><br></div><div>Regards,</div><div>Iftekhar</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Jul 8, 2014 at 2:10 PM, Tom Stellard <span dir="ltr"><<a href="mailto:tom@stellard.net" target="_blank">tom@stellard.net</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi<br>
<br>
Do the two 32-bit bases need to be stored in consecutive registers? If<br>
so, you could still use the 64-bit loads and then use REQ_SEQUENCE to create<br>
a pair of 32-bit registers.<br>
<span class="HOEnZb"><font color="#888888"><br>
-Tom<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
On Tue, Jul 08, 2014 at 01:46:30PM -0700, Iftekhar Chowdhury wrote:<br>
> Yes, the target does not have 64-bit GPRs. But it still needs to support<br>
> 64-bit address space.<br>
><br>
> Cheers,<br>
> Iftekhar<br>
><br>
><br>
> On Tue, Jul 8, 2014 at 1:19 PM, Hal Finkel <<a href="mailto:hfinkel@anl.gov">hfinkel@anl.gov</a>> wrote:<br>
><br>
> > ----- Original Message -----<br>
> > > From: "Iftekhar Chowdhury" <<a href="mailto:iftekhar.hc@gmail.com">iftekhar.hc@gmail.com</a>><br>
> > > To: <a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a><br>
> > > Sent: Tuesday, July 8, 2014 1:06:44 PM<br>
> > > Subject: [LLVMdev] Selection DAG node for 64-bit load<br>
> > ><br>
> > ><br>
> > ><br>
> > ><br>
> > ><br>
> > > Hi Fellow LLVM Experts,<br>
> > ><br>
> > > Currently, Selection DAG node for load seems to expect a 32-bit base<br>
> > > and an offset. Is it possible to extend load node definition to 2<br>
> > > 32-bit bases and an offset? Two 32-bit bases are supposed to<br>
> > > represent one 64-bit address.<br>
> > ><br>
> > ><br>
> ><br>
> > I don't understand why you're suggesting this? Does your target have a<br>
> > 64-bit address space but no 64-bit GPRs?<br>
> ><br>
> > -Hal<br>
> ><br>
> > ><br>
> > > Any suggestions, comments are much appreciated.<br>
> > ><br>
> > ><br>
> > ><br>
> > > Regards,<br>
> > ><br>
> > > Iftekhar<br>
> > > _______________________________________________<br>
> > > LLVM Developers mailing list<br>
> > > <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
> > > <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
> > ><br>
> ><br>
> > --<br>
> > Hal Finkel<br>
> > Assistant Computational Scientist<br>
> > Leadership Computing Facility<br>
> > Argonne National Laboratory<br>
> ><br>
<br>
> _______________________________________________<br>
> LLVM Developers mailing list<br>
> <a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu" target="_blank">http://llvm.cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br>
<br>
</div></div></blockquote></div><br></div>