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<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I'm not sure how to handle some of the trickier instruction encodings in MIPS64r6. My problem is that some instructions determine the operation based on the relationship between two fields. For example, 'beqc $rs, $rt, offset' (branch if
equal, no delay slot) and bovc (branch if addition would overflow, no delay slot) share the same major opcode and field layout. When the register number $rs is less than the register number $rt, it is a beqc instruction. When the register number $rs is greater
or equal to the register number $rt, it is a bovc.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Unsurprisingly, defining both of these instructions in tablegen causes decoding conflicts. Are there any targets with similar encoding/decoding issues that I could look at?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal" style="text-align:justify"><b><span style="font-size:12.0pt;font-family:"Arial","sans-serif";color:#3333FF">Daniel Sanders<o:p></o:p></span></b></p>
<p class="MsoNormal" style="text-align:justify"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#3333FF">Leading Software Design Engineer, MIPS Processor IP<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#3333FF">Imagination Technologies Limited<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify"><a href="http://www.imgtec.com/"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:blue">www.imgtec.com</span></a><span style="font-size:10.0pt;font-family:"Arial","sans-serif""><o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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