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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif"">Thanks. I found a few examples there that are fairly similar to my problem. It looks like I'll also need to put one of them in a separate DecoderNamespace to silence the
decoding conflict warning. Otherwise tablegen discards both instructions and the tablegen-erated code never calls the custom decoder method.<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Mihail Popa [mailto:mihail.popa@gmail.com]
<br>
<b>Sent:</b> 13 May 2014 14:39<br>
<b>To:</b> Daniel Sanders<br>
<b>Cc:</b> LLVM Developers Mailing List (llvmdev@cs.uiuc.edu)<br>
<b>Subject:</b> Re: [LLVMdev] Instructions with overlapping encodings that are disambiguated by field comparisons<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">Hi Daniel.<o:p></o:p></p>
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<p class="MsoNormal">Unfortunately this requires a custom decoder method. <o:p></o:p></p>
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<p class="MsoNormal">Take a look at the ARM back-end. There are plenty such examples.<br>
<br>
Mihai<o:p></o:p></p>
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<p class="MsoNormal">On 13 May 2014 12:47, Daniel Sanders <<a href="mailto:Daniel.Sanders@imgtec.com" target="_blank">Daniel.Sanders@imgtec.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Hi,<o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">I'm not sure how to handle some of the trickier instruction encodings in MIPS64r6. My problem is that some instructions determine the operation based on the relationship between
two fields. For example, 'beqc $rs, $rt, offset' (branch if equal, no delay slot) and bovc (branch if addition would overflow, no delay slot) share the same major opcode and field layout. When the register number $rs is less than the register number $rt, it
is a beqc instruction. When the register number $rs is greater or equal to the register number $rt, it is a bovc.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Unsurprisingly, defining both of these instructions in tablegen causes decoding conflicts. Are there any targets with similar encoding/decoding issues that I could look at?<o:p></o:p></p>
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<b><span style="font-family:"Arial","sans-serif";color:#3333FF">Daniel Sanders</span></b><o:p></o:p></p>
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<span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#3333FF">Leading Software Design Engineer, MIPS Processor IP</span><o:p></o:p></p>
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<span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#3333FF">Imagination Technologies Limited</span><o:p></o:p></p>
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<a href="http://www.imgtec.com/" target="_blank"><span style="font-size:10.0pt;font-family:"Arial","sans-serif"">www.imgtec.com</span></a><o:p></o:p></p>
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http://llvm.cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><o:p></o:p></p>
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