<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Apr 22, 2014 at 11:39 PM, Craig Topper <span dir="ltr"><<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">If memory serves the Xi16, Xi32, and Xi64 types cause some magic inside of BinOpMI_F(or classes it inherits from) to OR a 1 into the LSB of the opcode.</div>
<div class="gmail_extra"><br></div></blockquote><div><br></div><div>Thanks a lot, Craig!<br><br><br><br> <br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="gmail_extra">
<br><div class="gmail_quote"><div><div class="h5">
On Tue, Apr 22, 2014 at 6:45 AM, Jun Koi <span dir="ltr"><<a href="mailto:junkoi2004@gmail.com" target="_blank">junkoi2004@gmail.com</a>></span> wrote:<br></div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div><div class="h5">
<div dir="ltr"><div><div><div>hi,<br><br>at the moment, TEST instruction is defined with 0xf7 opcode, as demonstrated below.<br><br>$ echo "0xf7 0xc0 0x00 0x00 0x00 0x22"|./Release+Asserts/bin/llvm-mc -disassemble -arch=x86<br>
.section __TEXT,__text,regular,pure_instructions<br> testl $570425344, %eax ## imm = 0x22000000<br><br></div>however, i cannot find anywhere this F7 opcode is defined in lib/Target/X86/X86InstrArithmetic.td.<br>
</div>we only have TEST defined with F6 & other opcode like below.<br><br></div>any hint please?<br><br>thanks.<br><br><div><br>let isCompare = 1 in {<br> let Defs = [EFLAGS] in {<br> let isCommutable = 1 in {<br>
def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>;<br> def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>;<br> def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>;<br>
def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>;<br> } // isCommutable<br><br> def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;<br> def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>;<br>
def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>;<br> def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>;<br><br> def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;<br>
def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;<br> def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;<br> def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;<br>
<br> def TEST8mi : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>;<br> def TEST16mi : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>;<br> def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;<br>
def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;<br><br> // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the<br> // register class is constrained to GR8_NOREX.<br>
let isPseudo = 1 in<br> def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask),<br> "", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>;<br> } // Defs = [EFLAGS]<br>
<br> def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL,<br> "{$src, %al|al, $src}">;<br> def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX,<br> "{$src, %ax|ax, $src}">;<br>
def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX,<br> "{$src, %eax|eax, $src}">;<br> def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX,<br> "{$src, %rax|rax, $src}">;<br>
} // isCompare<br><br><br></div></div>
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<br></blockquote></div><span class="HOEnZb"><font color="#888888"><br><br clear="all"><div><br></div>-- <br>~Craig
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