<html><head><meta http-equiv="Content-Type" content="text/html charset=iso-8859-1"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Hi Christopher,<div><br></div><div><br><div><div>On Feb 27, 2014, at 3:22 AM, C. Bergström <<a href="mailto:cbergstrom@pathscale.com">cbergstrom@pathscale.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">I'm doing some per-processor tuning and hit a problem with the "MOV" family of instructions on Intel/AMD.<br>(This problem will likely also become very real for ARMv8 too though)<br>-----------<br><br>In the Intel/AMD case there exist MOV8rr and VMOVDQArr<br>Both use WriteMove SchedRW<br>But one wants 1 cycles and ALU, another 4 cycles and FPU for bulldozer<br>If we speak about itinerary classes, they have different - IIC_MOV and IIC_SSE_MOVA_P_RR<br>these classes in the old IProcessortinerary model give me the possibility to describe latency and resources exactly<br>So as I understand if I want new model, I need to add new WriteMovSSE for example<br></blockquote>That is a possibility if you think that distinction will likely benefit for several architectures. You would have to do the targeting of that new model for each architecture.</div><div><br><blockquote type="cite">Maybe they're just in progress<br>They pointed that it's possible to create InstRW where you put for example your new WriteMovSSE<br> and associated instructions without modifying the definition but I tried it - no impact (I need to double check this was tested with MI scheduler)<br></blockquote><div>Yes, you should be able to do that, see <span style="font-family: Menlo; font-size: 11px;">lib/Target/ARM/ARMScheduleSwift.td </span>for an example.</div><div>If you are not seeing anything, it may just mean the scheduler does not think there is something to change even with your new model.</div><div>You can check the actual scheduling model for each instruction by poking around *.inc files (i do not remember which one contains the actual information).</div><div><br></div><blockquote type="cite"><br>To work-around this I'm currently doing it both the "old way" and the new way...<br><br>Bug? Is the code in some transition phase? (maybe I'm doing it "wrong")<br><br>Any tips on how to get per-processor/per-vendor tuning would be most welcome<br></blockquote>Again, <span style="font-family: Menlo; font-size: 11px;">lib/Target/ARM/ARMScheduleSwift.td </span>should be a good example.</div><div><br></div><div>Thanks,</div><div>-Quentin<br><blockquote type="cite">_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a> <a href="http://llvm.cs.uiuc.edu">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a><br></blockquote></div><br></div></body></html>