<div dir="ltr">Hi,<div> An error instruction scheduling in post-ra schedule pass confused me a lot, I hack the code, </div><div>and found that maybe some bug in Alias Analysis while enable useAA(). The following is a </div>
<div>piece of IR I debuged:<br><div><i> <font size="1">EntryBB:</font></i></div><div><i><font size="1"> ...</font></i></div><div><i><font size="1"> 1 %uBase16 = bitcast %union.VR_union* %uu_buf to [8 x i16]*</font></i></div>
<div><i><font size="1"> 2 %arrayidx = bitcast %union.VR_union* %uu_buf to [8 x i16]*</font></i></div><div><i><font size="1"> 3 store i16 -1, i16* %arrayidx, align 16</font></i></div><div><i><font size="1"> 4 %arrayidx2 = getelementptr inbounds [8 x i16]* %uBase16, i32 0, i32 1</font></i></div>
<div><i><font size="1"> 5 store i16 4660, i16* %arrayidx2, align 2</font></i></div><div><i><font size="1"> ...(set the 128bit vector to uu_buf)</font></i></div><div><i><font size="1"> 6 %vecalign = bitcast %union.VR_union* %uu_buf to ppc_fp128</font></i></div>
<div><i><font size="1"><br></font></i></div><div><i><font size="1"> ; load 128bit vector from uu_buf</font></i></div><div><i><font size="1"> 7 %data = load ppc_fp128* %vecalign, align 16</font></i></div><div><i><font size="1"> ... </font></i></div>
<div><i><font size="1"> ... (other Basic blocks)</font></i></div><div><i><font size="1"><br></font></i></div><div><i><font size="1"> BB#4:</font></i></div><div><i><font size="1"> 8 store i16 1000, i16* %arrayidx, align 16</font></i></div>
<div><i><font size="1"> 9 <b>store i16 1234, i16* %arrayidx2, align 16</b></font></i></div><div><i><font size="1"> ... (set the 128bit vector to uu_buf)</font></i></div><div><i><font size="1"> 10 %vecalign = bitcast %union.VR_union* %uu_buf to ppc_fp128</font></i></div>
<div><i><font size="1"><br></font></i></div><div><i><font size="1"> ; load 128bit vector from uu_buf</font></i></div><div><i><font size="1"> <b>11 %data = load ppc_fp128* %vecalign, align 16</b></font></i></div><div>
<i><font size="1"> ....</font></i></div><div> According to my understanding, all the "store" instructons which set the uu_buf (e.g. NO.9) </div><div>should be "PartialAlias" with the load uu_buf instruction (NO.11). But after the "Codegen Prepare" </div>
<div>pass , the BB#4 will be transformed to something like:</div><div><i> <font size="1">BB#4:</font></i></div><div><i><font size="1"> ...</font></i></div><div><i><font size="1"> 1 %sunkaddr = ptrto %union.VR_union uu_buf to i64</font></i></div>
<div><i><font size="1"> 2 %sunkaddr23 = add i64 %sunkaddr, 2</font></i></div><div><i><font size="1"> <b> 3 %sunkaddr24 = inttoptr i64 %sunkaddr23, align 2</b></font></i></div><div><i><b><font size="1"> 4 store i16 1234, i16* %sunkaddr24, align 2</font></b></i></div>
<div><i><font size="1"> ...</font></i></div><div><i><font size="1"> 5 %vecalign = bitcast %union.VR_union* %uu_buf to ppc_fp128</font></i></div><div><i><font size="1"> <b> 6 %data = load ppc_fp128* %vecalign, align 16</b></font></i></div>
<div><i><font size="1"> ...</font></i></div><div> The Alias Analysis will return "NoAlias" for the NO.6 instruction and No.4 instruction (it should be PartialAlias).</div><div>Alias Analysis stop analysising on instruction NO.3, because %sunkaddr24 is not a pointer! </div>
<div> So, when the post-ra scheduler got "NoAlias" infomation, it would schedule instruction like:</div><div><i> <font size="1">BB#4:</font></i></div><div><i><font size="1"> ...</font></i></div><div><i><font size="1"> 1 %sunkaddr = ptrto %union.VR_union uu_buf to i64</font></i></div>
<div><i><font size="1"> 2 %sunkaddr23 = add i64 %sunkaddr, 2</font></i></div><div><i><font size="1"><br></font></i></div><div><i><font size="1"> <b>; Error schedule the load instruction to this location</b></font></i></div>
<div><font size="1"><i> </i><b><i>6 %data = load ppc_fp128* %vecalign, align 16</i> </b></font></div><div><i><font size="1"> 3 %sunkaddr24 = inttoptr i64 %sunkaddr23, align 2</font></i></div><div><i><font size="1"> 4 store i16 1234, i16* %sunkaddr24, align 2</font></i></div>
<div><i><font size="1"> ...</font></i></div><div><i><font size="1"> 5 %vecalign = bitcast %union.VR_union* %uu_buf to ppc_fp128</font></i></div><div><i><font size="1"> ...</font></i></div><div> And this is an error scheduling!</div>
<div> Has someone encountered this problem before?</div></div><div><br></div><div>Best Regards,</div><div>Yaorong Lee</div></div>