<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On Jan 7, 2014, at 10:47 AM, Jakob Stoklund Olesen <<a href="mailto:stoklund@2pi.dk">stoklund@2pi.dk</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><br>On Jan 7, 2014, at 10:40 AM, Evan Cheng <<a href="mailto:evan.cheng@apple.com">evan.cheng@apple.com</a>> wrote:<br><br><blockquote type="cite"><br>On Dec 30, 2013, at 8:40 PM, Chris Lattner <<a href="mailto:clattner@apple.com">clattner@apple.com</a>> wrote:<br><br><blockquote type="cite"><br>On Dec 30, 2013, at 4:17 PM, Hal Finkel <<a href="mailto:hfinkel@anl.gov">hfinkel@anl.gov</a>> wrote:<br><br><blockquote type="cite">----- Original Message -----<br><blockquote type="cite">From: "Craig Topper" <<a href="mailto:craig.topper@gmail.com">craig.topper@gmail.com</a>><br>To: "Chandler Carruth" <<a href="mailto:chandlerc@google.com">chandlerc@google.com</a>><br>Cc: "LLVM Developers Mailing List" <<a href="mailto:llvmdev@cs.uiuc.edu">llvmdev@cs.uiuc.edu</a>><br>Sent: Monday, December 30, 2013 2:29:50 PM<br>Subject: Re: [LLVMdev] Random question about the x86 backend (and backends<span class="Apple-tab-span" style="white-space: pre;"> </span>in general I suppose)<br><br><br><br>I can't speak directly to the questions themselves, but I'll ask a<br>couple back. When you say that some instructions are missing<br>mayLoad, do these instructions have patterns? Tablegen can infer<br>mayLoad/mayStores/hasSideEffects from patterns so it doesn't always<br>need to be listed explicitly in the td files.<br></blockquote><br>Having recently audited these flags in the PowerPC backend, I highly recommend looking at these from the *GenInstrInfo.inc file directly. I find this much easier. In theory, we'd like to move away from the pattern-based flag inference. Once a target is free of dependence on the inference rules, it can set bit guessInstructionProperties = 0; to turn them off completely (see class InstrInfo in Target.td).<br></blockquote><br>In MHO, we should try to avoid redundancy as much as possible. The only reason to have these flags is when instructions don't have patterns.<br></blockquote><br>I'm fairly certain that Jakob put in an error (warning?) when tablegen detects redundant flags.<br></blockquote><br>Tablegen will emit an error if the specified flags are inconsistent with the patterns.<br><br>If you clear the guessInstructionProperties flag, it will also refuse to infer flags from patterns, while still verifying the manually specified flags against the patterns when possible.<br></div></blockquote></div><br><div>I’d like to throw out that having the inference present can be a massive problem at time. It’s reasonably common to have a multi class that is reused for a number of different instructions, say different types of load. Some of the instantiations of the class have a pattern (say a normal i32 load) and some don’t (load of an illegal type, for example). In this case, you need to set the isLoad flag on the defs in the multiclass in order the make sure the latter get it properly, but you’ll get warnings (errors?) from tblgen about redundant flags on the former. The typical workaround is to duplicate the multiclass for with-flags and without-flags, which is even more useless duplication than having the flags ever was.</div><div><br></div><div>—Owen</div><div><br></div></body></html>